UNIVERSITAS INDONESIA PAPAN INFORMASI ELEKTRONIK DENGAN PS2 KEYBOARD TUGAS AKHIR EVY CHRISTANTO SRI NUGROHO

UNIVERSITAS INDONESIA

PAPAN INFORMASI ELEKTRONIK DENGAN PS2 KEYBOARD

TUGAS AKHIR

EVY CHRISTANTO SRI NUGROHO 07 06 19 9294

FAKULTAS TEKNIK PROGRAM STUDI TEKNIK ELEKTRO DEPOK JUNI, 2010

UNIVERSITAS INDONESIA

PAPAN INFORMASI ELEKTRONIK DENGAN PS2 KEYBOARD

TUGAS AKHIR

Diajukan sebagai salah satu syarat untuk memperoleh gelar Sarjana Teknik

EVY CHRISTANTO SRI NUGROHO 07 06 19 9294

FAKULTAS TEKNIK PROGRAM STUDI TEKNIK ELEKTRO DEPOK JUNI, 2010

HALAMAN PERNYATAAN ORISINALITAS

Tugas Akhir ini adalah hasil karya saya sendiri, Dan semua sumber baik yang dikutip maupun dirujuk Telah saya nyatakan dengan benar.

Nama NPM Tanda Tangan

: Evy Christanto Sri Nugroho : 0706199294 :

Tanggal

: 23 Juni 2010

ii

Universitas Indonesia

Papan informasi..., Evy Christian Sri Nugroho, FT UI, 2010

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KATA PENGANTAR / UCAPAN TERIMA KASIH

Puji syukur saya panjatkan kepada Tuhan Yang Maha Esa, karena atas berkat dan rahmat-Nya, saya dapat menyelesaikan tugas akhir ini. Penulisan tugas akhir ini dilakukan dalam rangka memenuhi salah satu syarat untuk mencapai gelar Sarjana Teknik Jurusan Elektro pada Fakultas Teknik Universitas Indonesia.. Oleh karena itu, saya mengucapkan terima kasih kepada: (1) Dr. Ir. Retno Wigajatri P.MS selaku dosen pembimbing yang telah menyediakan waktu, tenaga, ide dan pikiran untuk mengarahkan saya dalam penyusunan tugas akhir ini. (2) Kedua orangtua tercinta yang telah memberi dukungan dengan kasih sayang, Citra Huseni, Amd yang dengan sabar selalu mendoakan dan memberi semangat, serta Junior Ompusunggu, ST atas bimbingannya selama mengerjakan tugas akhir ini.

(3) Bapak panggung dan Bapak erisman, S.Si yang memberikan keleluasan waktu selama ini di PT Sanken Indonesia, serta Analisis dan repair group yang telah membantu tugas akhir ini sampai akhir.

Akhir kata, saya berharap Tuhan Yang Maha Esa berkenan membalas segala kebaikan semua pihak yang telah membantu. Semoga Tugas Akhir ini membawa manfaat bagi pengembangan ilmu.

Depok, 23 Juni 2010

Penulis

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HALAMAN PERNYATAAN PERSETUJUAN PUBLIKASI TUGAS AKHIR UNTUK KEPENTINGAN AKADEMIS =======================================================================================

Sebagai sivitas akademik Universitas Indonesia, saya yang bertanda tangan di bawah ini : Nama NPM Program Studi Departemen Fakultas Jenis karya

: Evy Christanto Sri Nugroho : 0706199294 : S1 – Ekstensi : Teknik Elektro : Teknik : Tugas Akhir

demi pengembangan ilmu pengetahuan, menyetujui untuk memberikan kepada Universitas Indonesia Hak Bebas Royalti Noneksklusif (Non-exclusive Royalty - Free Right) atas karya ilmiah saya yang berjudul : Papan Informasi Elektronik dengan PS2 Keyboard beserta perangkat yang ada (jika diperlukan). Dengan Hak Bebas Royalti Noneksklusif ini Universitas Indonesia berhak menyimpan, mengalih media / formatkan, mengelola dalam bentuk pangkalan data (database), merawat, dan memublikasikan tugas akhir saya tanpa meminta izin dari saya selama tetap mencantumkan nama saya sebagai penulis / pencipta dan sebagai pemilik Hak Cipta. Demikian pernyataan ini saya buat dengan sebenarnya. Dibuat di : Depok Pada tanggal : 23 Juni 2010 Yang menyatakan

( Evy Christanto Sri Nugroho )

v



ABSTRAK

Nama : Evy Christanto Sri Nugroho Program Studi : S1 - Ekstensi Judul : Papan Informasi Elektronik dengan PS2 Keyboard

Informasi tentang model yang sedang berada di line produksi PT Sanken Indonesia sangat dibutuhkan untuk mengoptimalkan kinerja personil bagian kontrol kualitas. Pada tugas akhir ini dilakukan rancang bangun papan informasi elektronik yang sesuai dengan kebutuhan dan memenuhi keterbatasan PT Sanken Indonesia. Papan informasi elektronik terdiri dari ATMega8535 sebagai pengolah dan peyimpan data, LCD untuk tampilan informasi tulisan bagi operator, power supply, dot matrix display serta melibatkan PS2 keyboard untuk memasukkan data. Dot matrix sebagai perangkat display dapat menampilkan tulisan bergeser dengan kriteria kecepatan looping 3.06s dan setiap karakter dapat dimunculkan dengan selang waktu sekitar 95ms. Perangkat ini juga mampu menyimpan data kendati terjadi hubungan putus listrik. Kata kunci: Papan Informasi Elektronik, Keyboard, dot matrix, ATMega8535, LCD

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ABSTRACT

Name : Evy Christanto Sri Nugroho Study Program: S1 - Ekstensi Title : Electronic Information Boards with PS2 Keyboard

Information about models which are running on the production line of PT. Sanken Indonesia is needed to optimize the performance of quality control personnel. In this project an electronic information board design for special purpose that suits the needs and meet the limitations of PT. Sanken Indonesia is conducted. Electronic information board is consist of ATMega8535 as data processing and storage, LCD to display text information for operators, power supply, dot matrix display and involves PS2 keyboard to enter data. Dot matrix display device can display the article shifts with speed loops 3,06s and each character can be raised at intervals of about 95ms. This device is also capable of storing data occurred despite broken electrical connection.

Keywords: Electronic Information board, Keyboard, dot matrix, ATMega8535, LCD

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DAFTAR ISI

JUDUL i PERNYATAAN ORISINALITAS ii HALAMAN PENGESAHAN iii UCAPAN TERIMA KASIH iv LEMBAR PERSETUJUAN PUBLIKASI KARYA ILMIAH v ABSTRAK vi ABSTRACT vii DAFTAR ISI viii DAFTAR GAMBAR x DAFTAR TABEL xi BAB I PENDAHULUAN ....................................................................... 1 1.1. Latar Belakang ................................................................................... 1 1.2. Tujuan Penulisan ................................................................................... 3 1.3. Pembatasan Masalah ....................................................................... 3 1.4. Metode Penulisan .................................................................................. 3 1.5. Sistematika Penulisan ............................................................................ 3 BAB II LANDASAN TEORI..................................................................... 5 2.1. Mikrokontroler ATMega8535............................................................... 3 2.1.1 Karakteristik mikrokontroler ATMega8535....................... 6 2.1.2 Peta Memori ATMega8535.................................................... 7 2.1.3 Register I/O............................................................................. 8 2.1.4 Interupsi.................................................................................. 9 2.2. PC Keyboard ...............................………….......................................... 11 2.3. Liquid Crystal Display (LCD).............................................................. 13 2.4. Dot Matrix LED 8x8............................................................................. 17 2.5. Pemrograman Mikrokontroler ATMega8535..................................... 20 BAB III PERANCANGAN PAPAN INFORMASI ELEKTRONIK...... 21 3.1 Perancangan Sistem ...............….........……........................................... 21 3.2. Rancang Bangun Perangkat.................................................................... 22 3.3. Perancangan dan Realisasi Perangkat Lunak (Software)........................25 3.4. Power Supply............................................................................................27 BAB IV PENGUJIAN PAPAN INFORMASI ELEKTRONIK.............. 28 4.1. Pengujian Power Supply............................................................... 28 4.2. Pengujian sistem minimum mikrokontroler ATMega8535.................... 29 4.3. Pengujian PS/2 keyboard ................................................................... 32 4.4. Data respon waktu.................................................................................. 33 4.5. Pengujian sistem secara keseluruhan..................................................... 38 BAB V KESIMPULAN............................................................................... 41 DAFTAR ACUAN....................................................................................... 42 LAMPIRAN..................................................................................................43

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DAFTAR GAMBAR

Gambar 1.1 : Line Produksi di PT Sanken Indonesia…………………… 2 Gambar 2.1 : Konfigurasi Pin ATmega8535………………….………… 6 Gambar 2.2 : Peta memori ATmega8535…………..………...............…. 7 Gambar 2.3 : Data Memori ………..............………………...…………… 8 Gambar 2.4 : Siklus interupsi pada ATmega8535….....……….....…….. 9 Gambar 2.5 : Register MCUCR….....................…………………………. 10 Gambar 2.6 : General Interrupt Control Register ……………….....…… 11 Gambar 2.7 : Konfigurasi dari tombol PC Keyboard …………………… 12 Gambar 2.8 : Sinyal Clock dan Data dari PC Keyboard……………….… 12 Gambar 2.9 : LCD 2x16......……………………………………………… 14 Gambar 2.10 : Flowchart inisialisasi LCD…………............……………… 17 Gambar 2.11 : Rangkaian Internal Dot matrix 8x8…..............…………… 18 Gambar 2.12 : Scanning Dot Matrix LED ……………………………… 19 Gambar 2.13 : Flowchart Scanning Dot Matrix LED ……………………. 19 Gambar 3.1 : Blok Diagram Perancangan Papan Informasi Elektronik…. 21 Gambar 3.2 : Rangkaian lengkap sistem papan pesan elektronik …..…… 22 Gambar 3.3 : Sistem minimum ATmega8535……................................… 22 Gambar 3.4 : Antarmuka PS/2 Keyboard dan ATmega8535……............. 24 Gambar 3.5 : Antarmuka LCD dan mikrokontroler ATmega8535…...….. 24 Gambar 3.6 : Shift-Register dan Dot Matrix Segment ….....................….. 25 Gambar 3.7 : Flowchart sistem secara umum …….....................................25 Gambar 3.8 : Flowchart mode input ………………......………………… 27 Gambar 3.9 : Rangkaian Power Supply………..........…………………… 27 Gambar 4.1 : Hasil simulasi dengan software AVR simulator pada LED..........................................................................… 31 Gambar 4.2 : Hasil output dengan menggunakan software AVR Simulator ……….............................................……… 32 Gambar 4.3 : Gambar gelombang antara data dengan clock pada keyboard ………..........……......……………… 33 Gambar 4.4 : Gelombang antara data pada keyboard dengan display dot matrix ………..........………………… 34 Gambar 4.5 : Respon waktu pemunculan karakter dari keyboard ……… 34 Gambar 4.6 : Clock data untuk satu karakter………… ………………… 35 Gambar 4.7 : Looping time dari program yang dibuat ………………… 35 Gambar 4.8 : Menu pilihan pada saat awal program dijalankan ……….…36 Gambar 4.9 : Tampilan LCD saat tidak menyala ……………...........…… 37 Gambar 4.10 : Tampilan setelah LCD menyala ………................…………37 Gambar 4.11 : Tampilan setelah mode “2” dipilih.......... ………………… 37 Gambar 4.12 : Tampilan judul setelah power on ……………...........…… 37 Gambar 4.13 : Tampilan menu ………........................................………… 38 Gambar 4.14 : Tampilan menu edit “1”......................... ………………… 38 Gambar 4.15 : Tampilan baca EEPROM ……………................……....... 38 Gambar 4.16 : Tampilan di display dot matrik .................………………… 38 ix



DAFTAR TABEL

Tabel 2.1 Tabel 2.2 Tabel 2.3 Tabel 2.4 Tabel 2.5 Tabel 2.6

Konfigurasi pin port ATMega8535............................................. Vektor Interupsi dan Reset.......................................................... Konfigurasi bit ISC11 dan ISC10................................................ Konfigurasi bit ISC01 dan ISC00............................................... Konfigurasi pin PC Keyboard..................................................... Konfigurasi pin LCD 2X16.........................................................

x

9 10 11 11 13 15



BAB I

PENDAHULUAN

1.1 Latar Belakang PT. Sanken Indonesia adalah perusahaan manufacture yang bergerak di bidang pembuatan power supply switching atau sering disebut dengan smps ( switching mode power supply) diantaranya, low power (adaptor untuk laptop, UPS), consumer produk atau biasa disebut dengan CP (televisi, radio, dvd, walkman, dll), dan office automation (untuk mesin photocopy, printer, komputer, dll). Semua jenis power supply tersebut dibuat secara massal dan dikerjakan oleh operator yang berada dalam suatu line produksi. Di PT Sanken Indonesia, terdapat 25 line produksi yang masing-masing membuat power supply lebih dari satu model. Rata-rata, dalam satu line dapat dibuat 6-15 model power supply selama 8 jam kerja secara kontinyu. Akibatnya, proses pergantian model jadi sangat cepat. Namun, dengan banyaknya model yang dibuat dan target produksi yang cukup tinggi, PT Sanken Indonesia juga dituntut untuk kualitas hasil produksi. Oleh karena itu, untuk setiap model senantiasa dilakukan pengecekan oleh staf atau operator bagian kontrol kualitas untuk periode tertentu baik di area produksi, final test elektrik, dan ekspor. Pada prakteknya, proses pergantian model yang cepat ini menimbulkan masalah yaitu staf ataupun operator bagian kontrol kualitas kesulitan mendeteksi pergantian model yang cepat. Akibatnya produk yang harusnya dilakukan proses selanjutnya terpaksa ditunda beberapa saat untuk keperluan pengecekan kualitas produk. Hal lebih lanjut, akan menghambat jadwal dari bisnis plan yang sudah dibuat.

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Walaupun pada masing-masing line produksi ada seorang leader produksi, namun mereka sangat sibuk mengatur pergantian material dan pengontrolan terhadap operator produksi, sehingga tidak mungkin untuk melaporkan pergantian model ini. Oleh karena itu dibutuhkan akses informasi yang cepat tentang pergantian model yang sedang diproduksi. Gambar 1.1 menunjukkan tidak adanya papan informasi didepan line produksi .

Gambar 1.1 Line produksi di PT.Sanken Indonesia

Papan informasi elektronik sebenarnya sudah banyak sekali dijual dipasaran, tetapi harga yang dimuat sangat mahal sektar 5-7 juta[11]. Selain itu, penggunaan papan informasi yang ada saat ini masih tergolong rumit dalam pengoperasiannya. Untuk mengubah isi pesan diperlukan sebuah komputer. Cara seperti ini membutuhkan waktu yang lama, kurang efektif dan membutuhkan area yang cukup besar. Area yang tersedia adalah 60cmx45cm. Bila harus menggunakan PC (personal computer), artinya harus menyediakan tempat untuk PC, sedangkan area yang ada tidak terlalu besar seperti yang dijelaskan diatas tadi. Disamping itu, daya listrik yang dibutuhkan relatif besar. Termotivasi oleh masalah tersebut pada skripsi ini dilakukan rancang bangun papan informasi elektronik yang isi pesannya dapat diinput dengan ps2 keyboard dan didesain khusus untuk area yang terbatas sehingga menjadi lebih ekonomis. Alat ini diharapkan mampu menampilkan pesan pada dotmatrik LED dan LCD sesuai dengan pesan yang diinput dari keyboard serta mampu menampilkan pesan berjalan sehingga dapat terlihat menarik bagi orang yang membacanya.



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1.2 Tujuan Penulisan Untuk mengatasi masalah yang telah disebutkan pada sub bab 1.1 maka pada tugas akhir ini dilakukan rancang bangun alat papan informasi elektronik yang disambungkan dengan PS/2 keyboard. 1.3 Pembatasan Masalah Pada tugas akhir ini, rancang bangun papan informasi elektronik dengan PS/2 keyboard dibatasi pada : 1.

Penggunaan display yang disesuaikan dengan area produksi.

2.

Penggunaan PS/2 keyboard sebagai input untuk karakter.

3.

Penggunaan software dengan bahasa C .

1.4 Metode Penulisan Metodologi penyelesaian masalah dalam pembuatan alat dan penyusunan laporan tugas akhir adalah: 1. Perancangan dan realisasi perangkat keras 1.

Penentuan jumlah karakter yang dibutuhkan.

2.

Menentukan ukuran alat yang disesuaikan dengan area produksi.

3.

Membuat program dengan menggunakan AVR Wizard Codevision.

2. Realisasi alat Setelah mendapat skema yang lebih rinci, mulai untuk menginventaris kebutuhan komponen sebagai perangkat kerasnya (hardware) dengan membuat daftar komponen dan kemudian mengadakannya. Selanjutnya, membuat layout PCB dan mencetaknya. Setelah pembuatan hardware selesai maka dilanjutkan dengan pembuatan perangkat lunak (software) untuk interfacing antar komponen-komponen perangkat kerasnya. 3. Uji coba Setelah pembuatan hardware & software dilakukan uji coba untuk mengetahui apakah alat dapat bekerja sesuai dengan yang diharapkan. 1.5 Sistematika Penulisan Pendahuluan berisikan tentang latar belakang masalah, perumusan masalah, tujuan, ruang lingkup proyek akhir, metodologi perancangan dan sistematika pembahasan laporan proyek akhir yang menerangkan sekilas tentang isi yang dikandung pada setiap bab dalam buku laporan ini. Universitas Indonesia


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BAB I Pendahuluan berisikan tentang latar belakang masalah, perumusan masalah, tujuan, batasan tugas akhir, metodologi perancangan dan sistematika pembahasan tugas akhir yang menerangkan dengan singkat tentang isi yang dikandung pada setiap bab buku ini. BAB II Landasan Teori berisikan tentang konsep-konsep dasar teori yang berhubungan dengan rancang bangun alat yang dibahas secara ringkas dan jelas, sehingga dapat digunakan sebagai penunjang pembuatan alat tersebut. BAB III Perancangan dan Realisasi membahas mengenai tahap-tahap perancangan dan realisasi sistem yang dibuat, dan metode yang dipakai dalam alat yang mencakup perancangan hardware dan software. BAB IV Pengujian dan Analisa menguraikan tentang pengujian sistem, yang berpengaruh terhadap kinerja sistem. Selain itu dicantumkan pula hasil pengukuran dan analisanya. BAB V Penutup berisikan kesimpulan dari perancangan alat yang telah direalisasikan berikut saran dalam pengembangan sistem dengan kelebihan dan kekurangannya.



BAB II LANDASAN TEORI

Sebelum melakukan rancang bangun, dibutuhkan tentang teori yang melandasi dari komponen-komponen rancang bangun seperti yang dijelaskan berikut ini 2.1

Mikrokontroler ATMega8535[1] Arsitektur mikrokontroler jenis AVR pertama kali dikembangkan pada

tahun 1996 oleh dua orang mahasiswa Norwegian Institute of Technology yaitu Alf-Egil Bogen dan Vegard Wollan. Mikrokontroler AVR kemudian dikembangkan lebih lanjut oleh Atmel. Seri pertama AVR yang dikeluarkan adalah mikrokontroler 8 bit AT90S8515, dengan konfigurasi pin yang sama dengan mikrokontroler 8051, termasuk address dan data bus yang termultipleksi. Mikrokontroler AVR menggunakan teknologi RISC dimana set instruksinya

dikurangi

dari

segi

ukurannya

dan

kompleksitas

mode

pengalamatannya. Pada awal era industri komputer, bahasa pemrograman masih menggunakan kode mesin dan bahasa assembly. Untuk mempermudah dalam pemrograman para desainer komputer kemudian mengembangkan bahasa pemrograman tingkat tinggi yang mudah dipahami manusia. Namun akibatnya, instruksi yang ada menjadi semakin komplek dan membutuhkan lebih banyak memori. Akibatnya siklus eksekusi instruksi ini menjadi semakin lama. Dalam AVR dengan arsitektur RISC 8 bit, semua instruksi berukuran 16 bit dan sebagian besar dieksekusi dalam 1 siklus clock. Berbeda dengan mikrokontroler MCS-51 yang instruksinya bervariasi antara 8 bit sampai 32 bit dan dieksekusi selama 1 sampai 4 siklus mesin, dimana 1 siklus mesin membutuhkan 12 periode clock. Dalam perkembangannya, AVR dibagi menjadi beberapa varian yaitu AT90Sxx, ATMega, AT86RFxx dan ATTiny. Pada dasarnya yang membedakan masing-masing varian adalah kapasitas memori dan beberapa fitur tambahan saja. 41



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2.1.1 Karakteristik ATMega8535 Fitur yang tersedia pada ATMega8535 adalah sebagai berikut : 

Frekuensi clock maksimum 16 MHz



Jalur I/O 32 buah, yang terbagi dalam PortA, PortB, PortC dan PortD



Analog to Digital Converter 10 bit sebanyak 8 input



Timer/Counter sebanyak 3 buah



CPU 8 bit yang terdiri dari 32 register



Watchdog Timer dengan osilator internal



SRAM sebesar 512 byte



Memori Flash sebesar 8 Kbyte dengan kemampuan read while write



Interrupt internal maupun eksternal



Port komunikasi SPI



EEPROM sebesar 512 byte yang dapat diprogram saat operasi



Analog Comparator



Komunikasi serial standar USART dengan kecepatan maksimal 2,5 Mbps

Konfigurasi dari pin ATMega8535 dapat dilihat pada Gambar 2.1.

Gambar 2.1 Konfigurasi pin ATMega8535[1]



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2.1.2 Peta Memori ATMega8535 ATMega8535 memiliki dua jenis memori yaitu data memory dan program memory ditambah satu fitur tambahan yaitu EEPROM memori untuk penyimpan data 

Program Memori ATMega8535 memiliki On-Chip In-System Reprogrammable Flash

Memory untuk menyimpan program. Untuk alasan keamanan, program memory dibagi menjadi dua bagian

Gambar 2.2 Peta memori ATMega8535[1]

yaitu Boot Flash Section dan Application Flash Section. Boot Flash Section digunakan untuk menyimpan program Boot Loader, yaitu program yang harus dijalankan pada saat AVR reset atau pertama kali diaktifkan. Application Flash Section digunakan untuk menyimpan program aplikasi yang dibuat user. AVR tidak dapat menjalankan program aplikasi ini sebelum menjalankan program Boot Loader. 

Data Memori Gambar 2.3 menunjukkan peta memori SRAM pada ATMega8535.

Terdapat 608 lokasi address data memori. 96 lokasi address digunakan untuk Register File dan I/O Memory sementara 512 lokasi address lainnya digunakan untuk internal data SRAM. Register File terdiri dari 32 general purpose working register, I/O register terdiri dari 64 register.



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Gambar 2.3 Data memori[1]



EEPROM Data Memori ATMega8535 memiliki EEPROM sebesar 512 byte untuk menyimpan

data. Lokasinya terpisah dengan sistem address register, data register dan control register yang dibuat khusus untuk EEPROM. 2.1.2 Register I/O Setiap port ATMega8535 terdiri dari 3 register I/O yaitu DDRx, Portx dan PINx. 

DDRx (Data Direction Register) Register DDRx digunakan untuk memilih arah pin. Jika DDRx = 1 maka

Pxn sebagai pin output Jika DDRx = 0 maka Pxn sebagai input. 

Portx (Port Data Register) Register Portx digunakan untuk 2 keperluan yaitu untuk jalur output atau

untuk mengaktifkan resistor pullup. 

PINx (Port Input Pin Address) Digunakan sebagai register input.

Untuk lebih jelas,perhatikan Tabel 2.1.



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Tabel 2.1 Konfigurasi pin port ATMega8535[1]

2.1.4 Interupsi Interupsi adalah kondisi yang memaksa mikrokontroler menghentikan sementara eksekusi program utama untuk mengeksekusi rutin interrupt tertentu/Interrupt Service Routine (ISR). Setelah melaksanakan ISR secara lengkap, maka mikrokontroler akan kembali melanjutkan eksekusi program utama yang tadi ditinggalkan. Gambar 2.4 menunjukkan saat program utama dikerjakan oleh mikrokontroler ATMega8535 kemudian tiba-tiba berhenti sementara waktu karena ada rutin lain yang harus ditangani oleh mikrokontroller ATMega8535, dan setelah selesai mengerjakan rutin tersebut mikrokontroler kembali mengerjakan instruksi pada program utama.

Gambar 2.4 Siklus interupsi pada ATMega8535[1]

Pada ATMega 8535 terdapat 21 sumber interupsi seperti yang dijelaskan pada Tabel 2.2.



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Tabel 2.2 Vektor Interupsi dan Reset[1]

Interupsi Eksternal Pada ATMega8535 terdapat 3 pin untuk interupsi eksternal, yaitu INT0, INT1, dan INT2. Interupsi eksternal dapat dibangkitkan apabila terdapat perubahan logika0 pada pin INT0, INT1, dan INT2. Pengaturan kondisi keadaan yang menyebabkan terjadinya interupsi eksternal diatur oleh register MCUCR (MCU Control Register), seperti Gambar 2.5 berikut.

Gambar 2.5 Register MCUCR[1]



Bit ISC11 dan ISC10 menentukan kondisi yang dapat menyebabkan interupsi eksternal pada pin INT1. Konfigurasi bit ISC11 dan ISC10 dapat dilihat pada Tabel 2.3 berikut.



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Tabel 2.3 Konfigurasi bit ISC11 dan ISC10[1]



Bit ISC01 dan ISC00 menentukan kondisi yang dapat menyebabkan interupsi eksternal pada pin INT0. Konfigurasi bit ISC01 dan ISC00 dapat dilihat pada Tabel 2.4 berikut. Tabel 2.4 Konfigurasi bit ISC01 dan ISC00[1]

Pemilihan interupsi eksternal diatur oleh register GICR (General Interupt Control Register), seperti dapat dilihat pada Gambar 2.6 berikut ini.

Gambar 2.6 General interupt control register[1]

Bit-bit INT0, INT1, dan INT2 pada register GICR digunakan untuk mengaktifkan masing-masing interupsi eksternal. Ketika bit-bit itu diset 1(aktif) maka interupsi eksternal akan aktif jika bit 1 (interrupt) pada SREG (status register) diset 1 juga (enable interrupt), instruksi untuk mengaktifkan interrupt yaitu sei. Program interupsi dari masing-masing interupsi akan dimulai dari vektor interupsi pada masing-masing jenis interupsi eksternal. 2.2 Keyboard Dalam beberapa proyek mikrokontroler, pemasangan keypad untuk input sudah cukup untuk dapat memasukkan data[4]. Akan tetapi, penggunaan pushbutton ataupun keypad ini memiliki keterbatasan, yaitu kedua fasilitas atau komponen memiliki jumlah tombol yang sedikit dan hanya dapat digunakan untuk pengambilan input data dalam jumlah yang terbatas. Universitas Indonesia


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Untuk mengatasi hal tersebut digunakan keyboard. Aplikasi penggunaan keyboard ini biasanya digunakan jika sebuah

keypad sudah tidak mampu

memenuhi kebutuhan karakter dari sistem yang dirancang. Misalnya pembuatan sebuah mesin ketik elektronik, moving character display (penampil karakter berjalan) dengan input keyboard, dan lain-lain.

Gambar 2.7 Konfigurasi data dari tombol keyboard[9]

Gambar 2.7 menunjukkan data dari masing-masing karakter tombol pada keyboard dalam heksadesimal. Jika karakter dari tombol di keyboard ditekan, maka data dikirimkan dalam bentuk sinyal data dan sinyal clock. Pengiriman satu paket data selalu diawali dengan start bit berlogika nol diikuti sinyal clock, dilanjutkan dengan 8 bit data yang dimulai dari bit 0 hingga bit ke 7, dan diakhiri dengan parity bit serta sebuah stop bit berlogika ‘1’. Setiap pengiriman bit data, baik pada start bit, 8 bit data, parity dan stop bit selalu diikuti dengan sebuah sinyal clock yang digunakan bagi bagian penerima bahwa satu bit data telah terkirim, keyboard membangkitkan sinyal clock dan pulsa clock pada umumnya yaitu 60-100μs

sebagaimana tercantum dalam pedoman menghubungkan

mikrokontroller dengan keyboard[9]. Perhatikan Gambar 2.8 berikut ini.

Gambar 2.8 Sinyal clock dan data dari keyboard[9]



13

Setelah bentuk data dikenali, kemudian dilanjutkan dengan pengenalan bentuk-bentuk kode (scancode) yang digunakan pada komunikasi data PC keyboard sebagai berikut: 

01H hingga 83H adalah scancode.



F0H sebagai awalan dari scancode menandakan ada tombol yang dilepas.



E0H sebagai awalan dari scancode tombol tambahan.



FAH, AAH, EEH, FFH, 00H yaitu kode-kode yang dipakai untuk menjawab perintah dari perangkat yang terhubung dengan keyboard. Setelah scancode dikenali, dilakukan perancangan program untuk

keyboard. Tahap awal merancang diagram alir (flowchart) dan program untuk pengambilan sebuah scancode yang berupa data PC keyboard serta program untuk konversi scancode tersebut ke dalam bentuk kode ASCII. Tipe socket keyboard yang digunakan dalam pembuatan tugas akhir ini adalah tipe PS2 / DIN6. Konfigurasi pin-pin daripada socket PS2 / DIN6 ini ditunjukkan oleh Tabel 2.5 berikut. Tabel 2.5 Konfigurasi pin Keyboard[9]

2.3 Liquid Crystal Display (LCD) Sarana peraga saat ini sudah sangat banyak, antara lain berupa Cathode Ray Tube (CRT), Liquid Crystal Display (LCD), dot matrix, seven-segment, dan lain sebagainya. Masing-masing peraga tersebut memiliki kelebihan dan kekurangan tergantung dari aplikasinya[12].

Teknologi LCD sudah banyak

digunakan dibandingkan teknologi CRT. Dibandingkan dengan CRT, LCD memiliki bentuk yang lebih ringan dan ringkas, konsumsi daya yang lebih kecil, Universitas Indonesia


14

radiasi yang lebih kecil, dan lebih nyaman dimata. Namun LCD juga memiliki kekurangan dibandingkan dengan CRT, diantaranya ketajaman gambar atau tulisan yang dihasilkan lebih kurang, hanya dapat bekerja pada satu macam resolusi, dan memiliki sudut pandang yang lebih kecil. LCD dapat digunakan untuk menampilkan karakter baik berupa huruf maupun angka. LCD memiliki ukuran yang bermacam-macam, seperti LCD dengan jumlah 1 – 4 baris, 16 – 40 karakter per baris, dan sebagainya. Salah satu contoh LCD tersebut adalah LCD 2x16. Gambar daripada LCD 2x16 ini ditunjukkan pada Gambar 2.9 berikut.

Gambar 2.9 LCD 2X16[7]

Pada umumnya, LCD memiliki 16 pin yang terdiri dari delapan pin jalur data (D0 – D7), tiga pin jalur kontrol (RS, E, dan RW), pin sumber tegangan dan ground, dan sebuah pin driver LCD dan dua pin backlight. Tabel 2.6 berikut menunjukkan konfigurasi dari pin-pin LCD tersebut.



15

Tabel 2.6 Konfigurasi pin LCD 2X16[7]

Untuk dapat mengatur tampilan LCD ini diperlukan karakter generator, yaitu bentuk-bentuk karakter yang dapat ditampilkan. Urutan dan posisi dari karakter yang akan ditampilkan dan pergantian ke display harus disimpan dan digabungkan disimpan di RAM. Semua pengontrol tampilan ini telah dibentuk dalam satu IC modul LCD yang berfungsi menerima kode-kode karakter (8-bit per karakter) dari suatu mikroprosesor atau komputer dan menyimpannya di display data RAM (DD RAM). Karakter ini akan dihubungkan dengan pola karakter yang tersedia pada karakter generator ROM (CG ROM). Jadi pola karakter yang dapat ditampilkan hanya pola karakter yang tersedia pada CG ROM. Namun, pemakai dapat mendefinisikan 8 pola (8-bit) tambahan yang disimpan di CG RAM. Module ini dapat menerima data atau instruksi dari mikroprosesor atau komputer dengan konfigurasi koneksi (interface) 4-bit atau 8-bit dan supply 5 volt. CG ROM mempunyai 160 (1280 byte) karakter yang disimpan dalam bentuk 7x5 dot matrix sehingga pola satu karakter disimpan dalam 8-bit. CG RAM dapat menyimpan 8 pola (64 byte) karakter tambahan. Sementara CG RAM mempunyai kapasitas 80 kode karakter (80 byte). Untuk menampilkan satu karakter, posisi data pada tampilan dikirim ke register instruksi diikuti kode karakter ke register data. Module LCD akan menghubungkan karakter dengan pola karakter pada CG ROM dam mengirimkan pola karakter pada display sesuai dengan posisinya. Posisi dari tampilan dapat dikurangi atau ditambah secara otomatis tergantung dari inisialisasi yang dilakukan sebelum mengisi karakter sehingga dapat mengirimkan karakter yang Universitas Indonesia


16

berurutan (string yang lebih dari satu karakter) dan akan ditampilkan satu string yang kontinyu. Penjelasan yang lebih detail mengenai LCD ini dapat dilihat pada lampiran yang berisikan datasheet LCD. Langkah yang perlu dilakukan sebelum menampilkan karakter pada LCD adalah melakukan inisialisasi LCD terlebih dahulu. Inisialisasi LCD adalah hal yang terpenting, jika inisialisasi gagal, maka tidak ada tampilan atau yang tampil pada LCD adalah karakter-karakter aneh. Pada tahap inisialisasi ini berisi konfigurasi dari LCD yang akan digunakan. Adapun konfigurasi yang harus diatur pada tahap inisialisasi ini adalah : 1. Banyaknya bit data interface dengan MPU yang digunakan (8 bit atau 4 bit). 2. Jumlah baris pada LCD yang digunakan. 3. Pergeseran cursor. 4. Pergeseran tampilan. 5. Cursor atau tanpa cursor, berkedip atau tidak berkedip. Diagram alir (flowchart) daripada inisialisasi LCD tersebut dapat dilihat pada Gambar 2.10. Contoh program untuk inisialisasi dan menampilkan string pada LCD dapat dilihat pada lampiran yang berisikan program untuk pengetesan LCD.



17

Gambar 2.10 Flowchart Inisialisasi LCD[8]

2.4 Dot Matrix LED 8x8 Sama halnya dengan LCD, dot matrix ini juga terdiri dari berbagai macam ukuran, salah satunya adalah dot matrix 8x8. Sesuai dengan namanya, komponen ini tersusun atas 64 buah LED (Light Emitting Diode), yang terdiri dari 8 baris dan 8 kolom. Dot matrix 8x8 ini memiliki rangkaian internal seperti yang ditunjukkan oleh Gambar 2.11 berikut.



18

Gambar 2.11 Rangkaian internal dot matrix 8x8[10]

Dot matrix yang ditunjukkan oleh Gambar 2.11, tersusun atas 64 buah LED berwarna merah. Untuk menyalakan sebuah LED dibutuhkan tegangan 2,5V dengan arus 20mA. Untuk menampilkan suatu karakter pada dot matrix tersebut tidak dapat dilakukan sekaligus, melainkan melalui proses scanning. Susunan data yang harus dikirimkan ke dot matrix dapat dilihat pada Gambar 2.12 dan untuk menampilkan karakter “I” prosesnya adalah sebagai berikut: 1. Kirim data 00h ke PORTA (port yang mengendalikan baris) dan PORTB (port yang mengendalikan kolom) diberi data 00h untuk kolom pertama. 2. Kemudian kirim data 41h ke PORTA dan 01h pada PORTB agar kolom kedua aktif. 3. Dan seterusnya diulangi beberapa kali. Dengan kecepatan scanning yang sangat cepat, akan tampak berupa satu huruf.



19

Gambar 2.12 Scanning dot matrix LED[1]

Flowchart untuk menampilkan sebuah karakter pada dot matrix LED ditunjukkan pada Gambar 2.13 berikut:

Gambar 2.13 Flowchart scanning dot matrix LED



20

2.5 Pemrograman Mikrokontroler ATmega8535 Untuk memaksimalkan fungsi perangkat yang dibuat dibutuhkan suatu program khusus. Untuk membuat program dibutuhkan juga software khusus yang berfungsi untuk membuat, mengcompile dan mendownload program ke mikrokontroller. AVRSTUDIO merupakan software khusus untuk bahasa assembly yang mempunyai fungsi sangat lengkap, yaitu digunakan untuk menulis program, kompilasi, simulasi dan download program ke IC mikrokontroler AVR. Sedangkan CodeVisionAVR merupakan software C-cross compiler, dimana program dapat ditulis dalam bahasa C, Codevision memiliki IDE (Integrated Development Environment) yang lengkap, dimana penulisan program, compile, link, pembuatan kode mesin (assembler) dan download program ke chip AVR dapat dilakukan pada codevision, selain itu ada fasilitas terminal, yaitu untuk melakukan komunikasi serial dengan mikrokontroler yang sudah di program. Keuntungan dalam menggunakan bahasa pemrograman C pada mikrokontroler, yaitu: 

Waktu pemrograman dan tes program relatif lebih pendek.



Pengetahuan terhadap instruksi set prosessor tidak terlalu dibutuhkan. Hanya pengetahuan dasar mengenai struktur memori CPU yang dibutuhkan, meskipun tidak terlalu penting.



Perincian seperti alokasi register, pengalamatan memori, dan tipe data telah diatur oleh compiler.



Memiliki kemampuan untuk mengkombinasikan variabel dengan operasi khusus sehingga dapat meningkatkan pembacaan program.



Program menjadi lebih terstruktur dan mudah dipahami, dan program dapat dibagi menjadi beberapa fungsi yang terpisah. Proses

download

program

ke

IC

mikrokontroler

AVR

dapat

menggunakan sistem download secara ISP (In-System Programming). In-System Programmable Flash on-chip mengizinkan memori program untuk diprogram ulang dalam sistem menggunakan hubungan serial SPI. Universitas Indonesia


BAB III Perancangan Papan Informasi Elektronik dengan PS/2 keyboard Setelah mempelajari komponen-komponen yang digunakan seperti yang sudah dijelaskan pada Bab 2, selanjutnya dilakukan proses perancangan seperti dijabarkan berikut ini. 3.1 Perancangan Sistem Pada perancangan ini komponen yang digunakan yaitu PS/2 keyboard, ATMega8535 sebagai sistem minimum, LCD dan dot matrix. Komponenkomponen tersebut memiliki fungsi tersendiri sesuai apa yang dijelaskan berikut ini. Tahap selanjutnya dilakukan perancangan seperti blok diagram dibawah ini.

Gambar 3.1 Blok diagram perancangan papan informasi elektronik dengan PS2 keyboard

Spesifikasi Alat 

Mikrokontroler ATMega8535 sebagai unit pemroses data.



8x8 Dot Matrix segment 8 buah.



Data karakter dapat disimpan pada EEPROM ATMega8535.



Tampilan keluaran bergeser ke kiri.



LCD alphanumeric 2x16 sebagai indicator pada mode edit.

41



22

3.2 Rancang Bangun Perangkat Rancang bangun perangkat keras meliputi beberapa bagian, yaitu: 

Perancangan sistem minimum menggunakan ATMega8535. Untuk menyimpan program dan sebagai pengendali terhadap keluaran yang diinginkan. Seperti telah diketahui, ATMega memiliki kemampuan untuk menyimpan data didalam EEPROM.



Perancangan antarmuka LCD 2x16 dengan mikrokontroler ATMega8535. LCD 2X16 ini digunakan untuk membaca tulisan yang akan diinputkan oleh keyboard.



Perancangan shift left register dan dot matrix LED Kedua komponen ini digunakan untuk menampilkan hasil tulisan yang diinput setelah disimpan ke EEPROM. Lalu tulisan akan digeser kekiri supaya terlihat lebih menarik.



Perancangan antarmuka PS/2 keyboard. Komponen ini digunakan untuk memberikan karakter huruf yang terdapat pada tombol keyboard yang ditekan sehingga akan terbentuk suatu tulisan. Rangkaian keseluruhan dari alat yang dibuat ditujukkan pada Gambar

3.2 sebagai lampiran A. Cara kerja dari rangkaian pada Gambar 3.2

adalah

sebagai berikut: ATMega8535 memiliki empat port yaitu Port A, Port B, Port C dan Port D. Pada skripsi ini PORTD disambungkan dengan clock dan data dari PS/2 keyboard, pengontrol LCD RS, R/W dan Enable. PORTA berfungsi sebagai data keluaran ke dot matrix LED, PORTC berfungsi sebagai 8-bit data keluaran ke LCD 2x16, sedangkan PORTB berfungsi untuk keluaran sinyal shift left register pada dot matrix LED. Gambar 3.3 berikut ini merupakan rangkaian sistem minimum ATMega8535.



23

Gambar 3.3 Sistem Minimum mengunakan ATMega8535

Selanjutnya PS/2 keyboard akan mengirimkan 2 buah sinyal keluaran berupa clock dan data. Pada saat tombol tersebut ditekan, maka clock dan data mengeluarkan pulsa sebanyak 11 bit. Pada umumnya sinyal clock dan pulsa clock yang dihasilkan dari keyboard yaitu 30-50 μs untuk low logic dan 30-50 μs untuk high logic. Pin clock pada PS/2 keyboard ini terhubung dengan interupsi eksternal mikrokontroler ATMega8535 PORTD.2 untuk mendeteksi ada atau tidaknya tombol keyboard yang ditekan, sedangkan pin data terhubung dengan PORTD.4. PS/2 keyboard terdiri 6 buah pin, tetapi hanya 4 buah pin yang terpakai yaitu: VCC, GND, clock, dan data. Pin VCC dan GND mendapat supply 5V. Gambar 3.4 berikut ini merupakan antarmuka PS/2 keyboard dengan sistem minimum ATMega8535.



24

Gambar 3.4 Antarmuka PS2 keyboard dengan ATMega8535[5]

Mikrokontroler ATMega8535 yang telah menerima data dari PS/2 keyboard memproses data tersebut dari scancode ke bentuk ASCII, lalu menampilkan data karakter yang diinput dari keyboard ke LCD 2x16 yang dikonfigurasikan menggunakan pengalamatan data 8-bit, yaitu pada PORTC.0 ~ PORTC.7. Mode 8-bit ini dipilih karena proses untuk menampilkan data pada LCD lebih cepat bila dibandingkan dengan mode 4-bit. Gambar 3.5 berikut ini merupakan antarmuka LCD dengan mikrokontroller ATMega8535.

Gambar 3.5 Blok antarmuka LCD dengan ATMega8535

Karakter-karakter yang telah diinput melalui keyboard disimpan dalam suatu tempat penyimpanan sementara atau register sehingga kumpulan karakterkarakter tersebut menjadi sekumpulan kata atau kalimat. Ketika tombol enter pada PS/2 keyboard di tekan, sekumpulan karakter tersebut disalin ke memori EEPROM pada mikrokontroler ATMega8535, lalu data tersebut dikeluarkan melalui PORTA untuk ditampilkan pada dot matrix LED dan tulisan digeser menggunakan komponen shift register.



25

Shift register ini merupakan serial to parallel shift register yang dikonfigurasikan sebagai shift left register (register geser kiri). Shift left register ini digunakan untuk scanning kolom pada dot matrix LED. Tampilan pada dot matrix LED ini menggunakan teknik scanning display, yaitu menyalakan tiap-tiap kolom secara bergantian dengan kecepatan yang sangat tinggi. Scanning display ini bertujuan untuk menghindari pembebanan arus pada rangkaian. Shift register ini menerima data berupa serial input, STCP, dan SHCP dari mikrokontroler ATMega8535 untuk memulai proses scanning display. Apabila pada suatu kolom bernilai logika “1” dan pada suatu baris bernilai logika “1”, maka dot matrix LED tersebut akan menyala. Untuk lebih jelas perhatikan Gambar 3.6 berikut ini.

Gambar 3.6 Shift register dan dot matrix segmen

3.3 Perancangan dan Realisasi Perangkat Lunak (Software) Perancangan perangkat lunak (software) dilakukan untuk mendukung kerja sistem berdasarkan hardware-nya, agar sistem dapat bekerja sesuai dengan fungsi dan aplikasinya. Bahasa pemrograman yang digunakan dalam perancangan dan pembuatan software sistem adalah bahasa tingkat tinggi, yaitu bahasa C untuk mikrokontroler seri Atmel AVR. Universitas Indonesia


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Software yang digunakan yaitu CodeVisionAVR 2.03.4 sebagai compiler bahasa C. Dengan software aplikasi ini, maka akan didapatkan file berekstensi (*.hex). File ini yang nanti akan di download pada Flash PEROM mikrokontroler ATMega8535, sebagai program untuk mengendalikan kinerja dari sistem yang dibuat. S tart

P esan P em b u k a T a m p il M e n u

A m b il K a r a k te r

Y K a ra k te r = ‘1 ’

In p u t M o d e

T

K a r a k te r = ‘ 2 ’

T

Y

K a r a k te r = 1 3 H

Y

T

B a ca D ata EEPROM

K a r a k te r = B ack sp ace

P esan K e s a la h a n

T

Y H apus 1 K a r a k te r

T a m p il K a r a k te r di LC D 2x16

T a m p il k e D o t M a tr ix

Gambar 3.7 Flowchart sistem secara umum



27

Gambar 3.8 Flowchart mode input

3.4 Power Supply Untuk menyalakan sistem dari alat yang dibuat, dibutuhkan catu daya +5V dc dengan current diatas 1A. Pada skripsi ini, power supply yang dibuat menggunakan IC regulator SI-8088HFE. Input yang dipakai menggunakan adaptor +19V dc. Gambar 3.9 berikut ini merupakan rangkaian power supply .

`Gambar 3.9 Rangkaian power supply[6]



BAB IV PENGUJIAN PAPAN INFORMASI ELEKTRONIK DENGAN PS2 KEYBOARD

Setelah dilakukan perancangan dan perakitan papan informasi ektronik dengan PS2 keyboard, tahap selanjutnya adalah menguji kinerja dari komponen maupun papan informasi elektronik dengan PS2 keyboard yang sudah dibuat. Pengujian yang dilakukan meliputi : 1. Pengujian keluaran power supply. 2. Pengujian sistem minimum mikrokontroler ATMega8535. 3. Pengujian pengiriman data scancode dari PS/2 keyboard ke mikrokontroler. 4. Pengambilan data waktu respon untuk pemunculan setiap karakter. 5. Pengujian sistem secara keseluruhan menampilkan pesan bergeser pada dot matrix LED. 4.1 Pengujian Power Supply Pengujian power supply dilakukan dengan mengukur tegangan +19Vdc pada bagian input dan tegangan +5Vdc pada bagian output seperti yang ditunjukkan pada Gambar 3.9. Pengukuran tegangan ini dimaksudkan untuk mengetahui kestabilan tegangan dioutput sehingga dapat mencatu sistem minimum dan dot matrix dengan maksimal. Titik-titik pengukuran adalah : a. Keluaran IC SI-8088HFE pin 2 Nilai tegangan keluaran

idealnya tergantung dari adjust di R1, karena

diinginkan tegangan +5Vdc maka R1 diatur sampai didapatkan nilai +5Vdc. Nilai tegangan yang didapat adalah 5,02V. b. Masukkan IC SI-8088HFE di pin 1 Nilai tegangan masukan IC SI-8088HFE adalah 19Vdc yang diambil dari adaptor. Nilai tegangan yang didapat adalah 18,98V.

41



29

4.2

Pengujian sistem minimum mikrokontroler ATMega8535 Pengujian terhadap sistem minimum ATMega8535 dilakukan untuk

mengetahui kinerja dari IC ATMega8535 terhadap program yang dibuat. Pengujian dilakukan dengan menjalankan program bahasa assembly atau bahasa tingkat tinggi lainnya seperti BASIC, C, PASCAL, dan lain-lain. Pada pengujian ini, digunakan bahasa C karena lebih portable dan fleksibel, memiliki daftar pustaka yang banyak, serta proses executable yang lebih cepat. Walaupun bagi pemula masih ada kesulitan dalam penggunaan pointer. Sebelum proses running program maka yang perlu dilakukan adalah mendownload

program

ke flash

PEROM

pada mikrokontroler.

Untuk

mendownload, terlebih dahulu mikrokontroler ini harus terkoneksi dengan downloader yang terhubung dengan USB port. Downloader yang digunakan adalah downloader USBasp ISP (In-System Programming). Untuk mengecek kesiapan sistem minimum untuk proses download, maka pada konsol window command prompt diberikan instruksi dengan format berikut ini :

Pengujian sistem dilakukan terhadap peripheral output dan input pada port I/O mikrokontroler. Pada pengujian ini program pengujian dibuat untuk melakukan beberapa variasi penyalaan LED pada port B. Listing program pengujian adalah:



30

Dari program di atas PORTB dari mikrokontroler ATMega8535 terhubung dengan kondisi aktif rendah. Dengan memberikan logika “0” pada PORTB, maka LED akan menyala. Pada program diatas, LED akan menyala pada PORTB secara bergiliran dengan selang waktu 0.5 detik dan dimulai dari LSB Universitas Indonesia


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(Least Significant Bit) sampai MSB (Most Significant Bit). Pergeseran bit terjadi pada saat terjadinya Timer Overflow sehingga menyebabkan aktifnya fungsi interupsi untuk menghitung waktu selama 0.5 detik. Dengan menggunakan software simulasi AVR Simulator, didapatkan keluaran berupa LED bergeser juga. Keluarannya dapat dilihat pada gambar 4.1berikut:

Gambar 4.1 Hasil simulasi dengan AVR simulator pada LED

Selanjutnya dilakukan pengujian terhadap LCD 2X16 untuk melihat apakah mikrokontroler juga sudah terkoneksi dengan benar dengan memberikan progam sehingga tampil tulisan “Hello Word”. 

Pengujian menampilkan karakter pada LCD 2x16 Pada pengujian ini, digunakan fungsi pustaka LCD.H pada perangkat

lunak CodevisionAVR 2.03.4 untuk inisialisasi LCD dan menambahkan intruksi lain untuk dapat menampilkan sebuah kalimat. Pengujian LCD 2x16 ini dilakukan dengan menampilkan kalimat “Hello World” pada LCD 2x16 dengan membuat program singkat berikut ini:



32

Dari program diatas, kalimat “Hello world” ditampilkan pada LCD 2x16 dengan posisi pada baris ke-2 dan dimulai dari kolom ke-1. Setelah program diatas di compile dan di download ke ATmega8535, ditunjukkan bahwa output kalimat tersebut beserta tata letaknya sesuai dengan yang diinputkan. Dengan menggunakan software AVR Simulator juga didapat hasil keluaran yang sama pada LCD. Hasil keluarannya dapat dilihat pada Gambar 4.2 dibawah ini:

Gambar 4.2 Hasil output dengan menggunakan avr simulator

4.3 Pengujian PS/2 keyboard Pengujian PS/2 keyboard ini bertujuan untuk mengetahui kinerja dari keyboard terhadap karakter yang ditekan pada tombol keyboard. Pengujian PS/2 keyboard dilakukan dengan mengukur parameter gelombang clock dan data yang berasal dari PS/2 keyboard. Pada pengujian ini, dilakukan dengan menekan tombol huruf “A” pada keyboard serta merekam gelombang output dari PS/2 keyboard menggunakan osiloskop dan ditunjukkan pada Gambar 4.3 berikut ini: Universitas Indonesia


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Gambar 4.3 Gambar gelombang antara data dengan clock pada keyboard

Dari gambar di atas dapat dilihat bahwa pada saat tombol “A” ditekan, gelombang clock (channel-2) berdetak sebanyak 11 clock sesuai dengan teori yaitu data tersebut dikirim secara serial dengan format: Start bit – Data – Parity check bit – stop bit. Selain itu, dari gambar 4.3 didapat bahwa clock yang dibutuhkan setiap karakter yang ditekan yaitu 920μs. Untuk satu clock dibutuhkan 83,63μs atau 11 KHz. Kemudian gelombang data (channel-1) menunjukkan nilai heksadesimal 0x1C (0001 1100). Jika dibandingkan dengan penjelasan prinsip kerja clock pada keyboard, hal ini masih memenuhi karakteristik keyboard dengan clock 60-100μs. Selain itu pula pada data tombol konfigurasi keyboard untuk huruf A adalah 1C (gambar 2.7). Data yang dikirim pertama kali yaitu mulai dari LSB hingga MSB. Data dengan nilai heksa 0x1C tersebut bukanlah merupakan data ASCII, tetapi data scancode. Oleh karena itu untuk dapat mengolah dan menampilkan karakter “A” tersebut pada LCD, maka scancode tersebut harus dikonversikan terlebih dahulu ke bentuk ASCII. Pengkonversian tersebut dilakukan dengan menggunakan program PS2 keyboard.



34

4.4 Data Waktu Respon Berikutnya adalah pengujian respon waktu. Data respon time diukur untuk mengetahui kecepatan waktu muncul diantara setiap karakter yang tampil pada display dot matrix baik karakter yang sama maupun yang berbeda. Dibawah ini merupakan data respon time yang diukur dengan osiloskop.

Gambar 4.4 Gelombang antara data pada keyboard dengan display dot matrik

Dari gambar 4.4 didapatkan bahwa respon time yang didapat untuk jeda waktu antara tombol enter ditekan dengan pemunculan karakter di display dot matrix adalah 85,2 ms.

Gambar 4.5 Respon waktu pemunculan karakter dari keyboard Universitas Indonesia


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Gambar 4.6 clock data untuk satu karakter

Dari hasil pengukuran data waktu respon antara pemunculan karakter pertama dengan karakter berikutnya pada keyboard memiliki respons time yang sama yaitu 95ms. Gambar 4.7 di bawah ini merupakan lamanya waktu untuk pemunculan dalam 1 siklus atau sering disebut dengan looping time.

Gambar 4.7 Looping time dari program yang dibuat Universitas Indonesia


36

Dari gambar diatas diatas didapatkan bahwa looping time yang didapatkan adalah 3.06s. Selain itu Gambar 4.7 dibawah ini merupakan waktu respon saat tombol enter ditekan pada keyboard sampai karakter itu muncul pada display dot matrix. Pengukuran ini diambil untuk mengetahui kecepatan waktu respon saat ditampilkan ke dot matrix.

4.5 Pengujian sistem secara keseluruhan Tahap akhir adalah pengujian sistem secara keseluruhan untuk mengetahui kinerja dari alat dan program keseluruhan yang dibuat sesuai pada lampiran A. Pada pengujian ini, alat yang telah dibuat dioperasikan dengan cara membuat string menu pilihan “1:Input Mode” dan “2:Read EEPROM”.

Gambar 4.8 Menu pilihan saat program dijalankan

Dengan menggunakan software AVR Simulator didapat hasil keluaran sesuai dengan program yang dibuat. Hasil keluarannya adalah muncul dua mode pada tampilan LCD yaitu mode input dan read EEPROM. Saat mode input, dapat dilakukan pengisian karakter dengan PS2 keyboard. Ketika ditekan tombol Enter, pada saat itu karakter yang telah diinput secara otomatis di simpan ke EEPROM dan pesan langsung ditampilkan ke dot matrix display. Untuk mengetahui data yang di input benar-benar telah disimpan dalam EEPROM, maka dilakukan pengujian dengan cara memutuskan hubungan sumber listrik dari alat ini, lalu kemudian menghubungkan sumber kembali. Pada menu awal tampilan LCD dipilih mode “Read EEPROM” dan lihat pada dot matrix display data terakhir yang disimpan tampil atau tidak. Dari

hasil

pengujian

ini,

ditunjukkan

bahwa

perangkat

dapat

menampilkan data terakhir yang tersimpan walau telah terjadi putusnya hubungan arus listrik seperti dapat dilihat pada Gambar 4.9 hingga 4.11. Universitas Indonesia


37

Gambar 4.9 Tampilan LCD saat tidak menyala

Saat sumber dimatikan, LCD tidak akan menampilkan tulisan seperti yang ditunjukkan pada gambar 4.9

Gambar 4.10 Tampilan setelah LCD menyala

Gambar 4.11 Tampilan setelah mode “2” dipilih

Saat sumber dinyalakan kembali tampilan seperti Gambar 4.10 akan tampil dan setelah dipilih mode “2” hasil tulisan yang diinput sebelum dimatikan sumber masih bisa terbaca. Urut-urutan tampilan perangkat secara keseluruhan dapat dilihat seperti pada Gambar 4.12 hingga 4.13.

Gambar 4.12 Tampilan judul setelah power on

Gambar 4.12 Menunjukkan bahwa saat power on, tampilan LCD menampilkan pesan pembuka.



38

Gambar 4.13 Tampilan menu

Setelah 0,5 s, tampilan pada LCD berubah menjadi mode pilihan yaitu mode input dan mode read EEPROM. Gambar 4.13 Menunjukkan tampilan menu setelah pesan pembuka.

Gambar 4.14 Tampilan menu edit “1”

Menu edit “1” atau pilihan mode input digunakan untuk menuliskan pesan atau informasi sesuai yang ditunjukkan pada Gambar 4.14.

Gambar 4.15 Tampilan baca EEPROM

Gambar 4.15 Menunjukkan tampilan setelah disimpan ke EEPROM atau setelah tombol enter ditekan.

Gambar 4.16 Tampilan di display dot matrik



39

Setelah itu hasil ditampilkan pada dot matrix display, sesuai dengan pesan yang diinputkan pada saat mode input dipilih. Gambar 4.16 menunjukkan hasil tampilan di dot matrix display. Dengan demikian, pengujian alat dan program secara keseluruhan dapat bekerja dengan baik dan sesuai dengan yang diharapkan.



BAB V KESIMPULAN Setelah melakukan rancangan bangun dan pengujian papan informasi elektronik dengan PS2 keyboard dapat disimpulkan bahwa : 1. Telah berhasil dilakukan rancang bangun papan informasi elektronik yang compact, mudah dioperasikan dan ekonomis yang didesain khusus untuk kebutuhan produksi PT Sanken Indonesia. 2. Papan pesan elektronik ini membutuhkan daya 1,25 watt, mampu menampilkan karakter ke LCD dari keyboard dengan kecepatan 95ms. 3. Waktu yang dibutuhkan untuk menampilkan tulisan ke display dot-matrik sekitar 85,2ms sedangkan untuk looping pemunculan karakter sekitar 3.06s.

41



DAFTAR ACUAN

1. Andrianto, Heri. (2008). Pemrograman Mikrokontroler AVR ATmega16 Menggunakan Bahasa C (CodeVision AVR). Bandung: Informatika. 2. Pappas, C.H., & Murray, W.H. Borland C++ Handbook (3rd ed.). Osborne: McGraw-Hill. 3. Glibota, Zvonko. (2004). DIY Moving Message Display. January 3, 2004. http://www.edaboard.com/ftopic58756.html/ 4. Hartanto, Budi. (2007). Memahami Logika Pembuatn Program C Secara Mudah. Yogyakarta: Andi Offset. 5. Soebhakti, Hendawan. (2007). Basic AVR Microcontroller Tutorial ATmega8535L. Batam: Politeknik Batam. 6. Haiduc, Pavel. (2008). CodeVisionAVR Version 2.03.4 User Manual. HP InfoTech 7. http://www.dipmicro.com/store/LCD-1602A-B 8. Datasheet LCD HD744840 9. Datasheet Keyboard 10. Datasheet Dot Matrix 11. http://indonetwork.or.id/alloffers/LED-MATRIX.html 12. http://home.iae.nl/users/pouweha/lcd/lcd0.shtml#pin_assignment

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NC NC

D DS4

VCC

14 DS3

10 11 SHCP

DS3

14 DS2

VCC

13 12 STCP

10 11 SHCP

13 12 STCP

DS2

14 DS1

10 11 SHCP

13 12 STCP

DS1

SER

G RCK

SRCLR SRCK

15 1 2 3 4 5 6 7 9

15 1 2 3 4 5 6 7 9

15 1 2 3 4 5 6 7 9

U6 SN74HC595

QA QB QC QD QE QF QG QH QH1

SER

SRCLR SRCK

G RCK

U5 SN74HC595


SER

G RCK

SRCLR SRCK

U4 SN74HC595


SER

G RCK

SRCLR SRCK

U3 SN74HC595

J4

DATA VCC

C J2

9 14 8 12 1 7 2 5

VCC

D0 D1 D2 D3 D4 D5 D6 D7

9 14 8 12 1 7 2 5

DM1

D0 D1 D2 D3 D4 D5 D6 D7

9 14 8 12 1 7 2 5

D0 D1 D2 D3 D4 D5 D6 D7

9 14 8 12 1 7 2 5

VCC

14 DS6

13 12 STCP

VCC

14 DS5

10 11 SHCP

13 12 STCP

VCC

14 DS4

10 11 SHCP

13 12 STCP

VCC

DM4

13 12 STCP

DM3

Power

C

DM2

1 2

10 11 SHCP

VCC

D0 D1 D2 D3 D4 D5 D6 D7

VCC

14 DS7

R1 POT1

10 11 SHCP

DS SHCP STCP

1 2 3

R2 470

13 3 4 10 6 11 15 16

13 3 4 10 6 11 15 16

13 3 4 10 6 11 15 16

ULN2803A(18)

13 3 4 10 6 11 15 16

7 8 9 10 11 12 13 14 C0 C1 C2 C3 C4 C5 C6 C7

D0 D1 D2 D3 D4 D5 D6 D7

15 16

4 5 6

D0 D1 D2 D3 D4 D5 D6 D7

ROW

18 17 16 15 14 13 12 11

OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8


IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 IN 8 DIODE CLAMP

15 1 2 3 4 5 6 7 9

1 2 3 4 5 6 7 8 10

1 2 3 4 5 6 7 8

D5 D6 D7

RS RW E

VSS VDD Vo 1 2 3

VCC

U2

J1

U1A 2x16 LCD (Hitachi HD44780 compatible)

VCC

14 DS

D

10 11 SHCP

13 12 STCP

LAMPIRAN A

B

RESET

9

JP1 1 2 3 4 5 6

S

D4

13

GND VCC D2

12

X2

PORT B J7

32 31 30

AREF AGND AVCC

X1

1 2 3 4 5 6 7 8

C0 C1 C2 C3 C4 C5 C6 C7

ATMEGA8535_DIP40

1 2 3 4 5 6 7 8

SER

G RCK

SRCLR SRCK

U10 SN74HC595

15 1 2 3 4 5 6 7 9


SER

SRCLR SRCK

G RCK

15 1 2 3 4 5 6 7 9


SER

G RCK

SRCLR SRCK

15 1 2 3 4 5 6 7 9


SER

G RCK

SRCLR SRCK

QA QB QC QD QE QF QG QH QH1 15 1 2 3 4 5 6 7 9

U9 SN74HC595

13 3 4 10 6 11 15 16

PC0 PC1 PC2 PC3 PC4 PC5 (TOSC1) PC6 (TOSC2) PC7

RESET

Y1

PS2-6PIN

VCC

PD0 (RXD) PD1 (TXD) PD2 (INT0) PD3 (INT1) PD4 (OC1B) PD5 (OC1A) PD6 (ICP) PD7 (TOSC2)

PORT A J6 B0 B1 B2 B3 B4 B5 B6 B7

U8 SN74HC595

13 3 4 10 6 11 15 16

C1 0.1nF

C0 C1 C2 C3 C4 C5 C6 C7

U7 SN74HC595

13 3 4 10 6 11 15 16

S1

22 23 24 25 26 27 28 29

1 2 3 4 5 6 7 8

DS7

14 15 16 17 18 19 20 21

(ADC0) PA0 (ADC1) PA1 (ADC2) PA2 (ADC3) PA3 (ADC4) PA4 (ADC5) PA5 (ADC6) PA6 (ADC7) PA7

A0 A1 A2 A3 A4 A5 A6 A7

DS6

D0 D1 D2 D3 D4 D5 D6 D7

RESET

PB0 (T0) PB1 (T1) PB2 (AIN0) PB3 (AIN1) PB4 (SS) PB5 (MOSI) PB6 (MISO) PB7 (SCK)

40 39 38 37 36 35 34 33

DS5

1 2 3 4 5 6 7 8

GND

R3 1k

B0 B1 B2 B3 B4 B5 B6 B7

11

VCC

A0 A1 A2 A3 A4 A5 A6 A7

13 3 4 10 6 11 15 16

10

J5 U11

B D0 D1 D2 D3 D4 D5 D6 D7

9 14 8 12 1 7 2 5

D0 D1 D2 D3 D4 D5 D6 D7 DM5

9 14 8 12 1 7 2 5

D0 D1 D2 D3 D4 D5 D6 D7 DM6

9 14 8 12 1 7 2 5

D0 D1 D2 D3 D4 D5 D6 D7 DM7

9 14 8 12 1 7 2 5 DM8

PORT C J8 J3

VCC 1 2

Power

7.3728MHz C2 22pF

VCC C3 22pF

JP2 B5

1 3 RESET 5 B7 7 B6 9 AVR-ISP

2 4 6 8 10

D0 D1 D2 D3 D4 D5 D6 D7

1 2 3 4 5 6 7 8 PORT D

A

A

Title

Sistem Minimum ATmega8535

Size

Number

Revision

A3 Date: File:


22-Sep-2010 Sheet of D:\Documents from C\Sistem Minimum.ddbDrawn By:

Evy Christanto

Lampiran B

Listing Program

// PAPAN INFORMASI ELEKTRONIK DENGAN PS/2 KEYBOARD SEBAGAI INPUT #include <mega8535.h> #include <delay.h> #include <matrix.h> //referensi keyboard #define KBD_CLOCK PORTD.2 #define KBD_DATA PIND.4 #define BUFF_SIZE 64 // referensi LCD #define LCD_RS PORTD.5 #define LCD_RW PORTD.6 #define LCD_E PORTD.7 #define COMMAND_MODE 0 #define DATA_MODE 1 #define WRITE_MODE 0 #define READ_MODE 1 #define LCD_PORT PORTC // LED Display #define SCROLL_DELAY

140

// Konstanta Kecepatan

// fungsi-fungsi void lcd_init(void); void lcd_clear(void); void lcd_putc(unsigned char ch); void lcd_putsf(unsigned char flash *); void lcd_puts(unsigned char *str); void put_char_kbbuff(unsigned char); void put_scancode_kbbuff(unsigned char); int getchar(void); int kbhit(void); void decode(unsigned char); void enable(void); // fungsi untuk enable LCD void goto_address(unsigned char a); void display_char(unsigned char data); void welcome_message(void); void input_mode(void); void menu_display(void);



void wrong_option(void); void displaying_message(void); void display_matrix(void); // variabel global unsigned char bitcount; unsigned char kb_buffer[BUFF_SIZE]; unsigned char buffcnt = 0; unsigned char *inpt, *outpt; unsigned char chcount; // Character counter // char message_matrix[]; // unsigned int matrix_content; // int char_count_disp, col_matrix; unsigned char message[100];



eeprom unsigned char message_matrix[100]; eeprom unsigned char last_address;

// keyboard scan codes (without & with shift key pressed) flash unsigned char unshifted[67][2] = { //0x0d,9, 0x0e,'`',0x15,'q',0x16,'1',0x1a,'z',0x1b,'s',0x1c,'a',0x1d,'w',0x1e,'2',0x21,'c',0x22,'x' ,0x23,'d',0x24,'e', 0x25,'4',0x26,'3',0x29,' ',0x2a,'v',0x2b,'f',0x2c,'t',0x2d,'r',0x2e,'5',0x31,'n',0x32,'b',0x33,'h',0x34,'g', 0x35,'y',0x36,'6',0x39,',',0x3a,'m',0x3b,'j',0x3c,'u',0x3d,'7',0x3e,'8',0x41,',',0x42,'k', 0x43,'i',0x44,'o', 0x45,'0',0x46,'9',0x49,'.',0x4a,'/',0x4b,'l',0x4c,';',0x4d,'p',0x4e,'',0x52,'`',0x54,'[',0x55,'=',0x5a,13, 0x5b,']',0x5d,'/',0x61,'<',0x66,8, 0x69,'1',0x6b,'4',0x6c,'7',0x70,'0',0x71,',',0x72,'2',0x73,'5',0x74,'6', 0x75,'8',0x79,'+',0x7a,'3',0x7b,'-',0x7c,'*',0x7d,'9',0,0 };

flash unsigned char shifted[67][2] = { //0x0d,9, 0x0e,'`',0x15,'Q',0x16,'!',0x1a,'Z',0x1b,'S',0x1c,'A',0x1d,'W',0x1e,'@',0x21,'C',0x2 2,'X',0x23,'D',0x24,'E', 0x25,'$',0x26,'#',0x29,' ',0x2a,'V',0x2b,'F',0x2c,'T',0x2d,'R',0x2e,'%',0x31,'N',0x32,'B',0x33,'H',0x34,'G', 0x35,'Y',0x36,'^',0x39,'L',0x3a,'M',0x3b,'J',0x3c,'U',0x3d,'&',0x3e,'*',0x41,'<',0x4 2,'K',0x43,'I',0x44,'O', 0x45,')',0x46,'(',0x49,'>',0x4a,'?',0x4b,'L',0x4c,':',0x4d,'P',0x4e,'_',0x52,'"',0x54,'{', 0x55,'+',0x5a,13, 0x5b,'}',0x5d,'|',0x61,'>',0x66,8, 0x69,'1',0x6b,'4',0x6c,'7',0x70,'0',0x71,',',0x72,'2',0x73,'5',0x74,'6', 0x75,'8',0x79,'+',0x7a,'3',0x7b,'-',0x7c,'*',0x7d,'9',0,0 }; // fungsi inisialiasi LCD void lcd_init(void) { delay_ms(50); LCD_E = 0; LCD_RS = COMMAND_MODE; LCD_RW = WRITE_MODE; delay_ms(1); LCD_PORT = 0x38; // jalur data 8 bit, 2 lines, huruf ukuran 5x8 ==> function set enable(); LCD_PORT = 0x0f; // display ON, kursor ON, kursor berkedip enable();


LCD_PORT = 0x06; enable(); lcd_clear(); }

// entry mode, increment, not shifted

// fungsi menghapus layar LCD void lcd_clear(void) { LCD_RS = COMMAND_MODE; LCD_PORT = 0x01; // clear LCD enable(); } void enable(void) { LCD_E = 1; delay_ms(1); LCD_E = 0; delay_ms(2); } //Rutin service interupsi untuk eksternal interrupt 0 (EXT_INT0) interrupt [2] void keyboard_isr(void) { static unsigned char data; // Rutin entered at falling edge // fungsi dipanggil pada saat sinyal KBD_CLOCK transisi turun // jika data bit adalah bit berikutnya yang akan dibaca // (bit 3 sampai 10 adalah data, start, stop & parity bis diabaikan if((bitcount < 11) && (bitcount > 2)) { data = (data >> 1); if (KBD_DATA) // jika bit berikutnya adalah 1 data = data | 0x80; // simpan bit '1' else data = data & 0x7f; // jika tidak simpan bit '0' } if(--bitcount == 0) { // Apakah semua bit sudah diterima ? decode(data); // decode byte yang diterima bitcount = 11; } } //*********************************************** // return 1 if a key is pressed (non blocking) // else return 0 int kbhit(void) { if (buffcnt) {


// reset buffer variables (flush the buffer) inpt = kb_buffer; outpt = kb_buffer; buffcnt = 0; bitcount = 11; return 1; } return 0; } // puts scan code (in hex format) into keyboard buffer // (used for debugging purposes) //*********************************************** void put_scancode_kbbuff(unsigned char sc) { unsigned char h,l; // convert hi and low nibbles of the scancode // into ascii and store them into keyboard buffer h = ((sc & 0xf0 ) >> 0x04) & 0x0f; if ( h > 9) h = h + 7; h = h + 0x30; put_char_kbbuff(h); l = sc & 0x0f; if ( l > 9) l = l + 7; l = l + 0x30; put_char_kbbuff(l); } //*********************************************** // store character in the keyboard ring buffer void put_char_kbbuff(unsigned char c) { if (buffcnt < BUFF_SIZE) { // if buffer is not full *(inpt++) = c; buffcnt++; if (inpt >= kb_buffer + BUFF_SIZE) // pointer wrapping inpt = kb_buffer; } } //*********************************************** // get next available character from the keyboard ring buffer // (waits until a character is available in the buffer) int getchar(void) { int byte;


while (buffcnt == 0); // wait for data byte = *outpt; // get byte outpt++; if (outpt >= kb_buffer + BUFF_SIZE) // pointer wrapping outpt = kb_buffer; buffcnt--; // decrement buffer count return byte; } //*********************************************** // decode scan code void decode(unsigned char sc) { static unsigned char is_up=0, shift = 0, mode = 0; unsigned char i; if (!is_up) { switch (sc) { case 0xF0 :// The up-key identifier is_up = 1; break; case 0x12 :// Left SHIFT shift = 1; break; case 0x59 :// Right SHIFT shift = 1; break; case 0x05 :// F1 if(mode == 0) mode = 1;// Enter scan code mode if(mode == 2) mode = 3;// Leave scan code mode break; default: if(mode == 0 || mode == 3) {// If ASCII mode if(!shift) {// If shift not pressed, do a table look-up for(i = 0; unshifted[i][0]!=sc && unshifted[i][0]; i++); if (unshifted[i][0] == sc) { put_char_kbbuff(unshifted[i][1]); } } else {// If shift pressed


for(i = 0; shifted[i][0]!=sc && shifted[i][0]; i++); if (shifted[i][0] == sc) { put_char_kbbuff(shifted[i][1]); } } } else put_scancode_kbbuff(sc);

// scan code

mode (debugging mode) break; } } else { is_up = 0;// Two 0xF0 in a row not allowed switch (sc) { case 0x12 :// Left SHIFT shift = 0; break; case 0x59 :// Right SHIFT shift = 0; break; case 0x05 :// F1 -- F1 puts you in debugging mode // pressing F1 again gets you out of debugging mode // in debugging mode hex code of the scan codes // are stored in the buffer instead of their ascii codes if(mode == 1) mode = 2; if(mode == 3) mode = 0; break; } } } void goto_address(unsigned char a) { LCD_RS = COMMAND_MODE; LCD_RW = WRITE_MODE; if (a>15) a = a + 0x30; LCD_PORT = a + 0x80; LCD_E = 1; delay_ms(1); LCD_E = 0; delay_ms(2); }


void display_char(unsigned char data) { LCD_RS = DATA_MODE; LCD_RW = WRITE_MODE; LCD_PORT = data; enable(); } //*********************************************** // display char on lcd void lcd_putc(unsigned char ch) { LCD_RS = DATA_MODE; LCD_PORT = ch; LCD_E = 1; delay_us(40); LCD_E = 0; delay_us(40); } //*********************************************** // display string on lcd // input: pointer to string stored in flash ROM void lcd_putsf(unsigned char flash *str) { while (*str!= '\0') { lcd_putc(*(str++)); } } //************************************************ // same as above except the string is in RAM void lcd_puts(unsigned char *str) { while (*str!= '\0') { lcd_putc(*(str++)); } } //************************************************ // Welcome Message void welcome_message(void) { unsigned char welcome1[] = "INFO BOARD"; unsigned char welcome2[] = "By:Evy.CH"; unsigned char i, j; i = 0; goto_address(1);


for (j=0; j<13; j++) { display_char(welcome1[i++]); } i = 0; goto_address(23); for (j=0; j<9; j++) { display_char(welcome2[i++]); } delay_ms(5000); lcd_clear(); } //************************************************* // Display Menu void menu_display(void) { unsigned char menu1[] = "1:Input Mode"; unsigned char menu2[] = "2:Read EEPROM"; unsigned char i, j; LCD_RS = COMMAND_MODE; LCD_RW = WRITE_MODE; LCD_PORT = 0x0c; enable(); i = 0; goto_address(0); for (j=0; j<12; j++) { display_char(menu1[i++]); } i = 0; goto_address(16); for (j=0; j<13; j++) { display_char(menu2[i++]); } } void wrong_option(void) { unsigned char wrong[] = "Sorry,"; unsigned char wrong1[] = "Wrong Option..."; unsigned char i, j; LCD_RS = COMMAND_MODE;


LCD_RW = WRITE_MODE; LCD_PORT = 0x0c; enable(); lcd_clear(); i = 0; goto_address(0); for (j=0; j<6; j++) { display_char(wrong[i++]); } i = 0; goto_address(16); for (j=0; j<15; j++) { display_char(wrong1[i++]); } delay_ms(2000); } void displaying_message(void) { unsigned char display[] = "Displaying"; unsigned char display1[] = "Message......"; unsigned char i; LCD_RS = COMMAND_MODE; LCD_RW = WRITE_MODE; LCD_PORT = 0x0c; enable(); lcd_clear(); // i = 0; goto_address(0); for (i=0; i<10; i++) { display_char(display[i]); } // i = 0; goto_address(16); for (i=0; i<13; i++) { display_char(display1[i]); } }


void input_mode(void) { // unsigned char message[100]; unsigned char ch, b, c, x, y, d; unsigned char i, j; lcd_init(); while(1) { ch = 0x00; chcount = 0; i = 0; b = 0; x = 0; d = 0; // fill the array with 4 empty spaces at the start and the end of the message // as the screen has 4 chars // (it looks better if we start scrolling with empty screen and end // with empty screen , rather than displaying four chars immediatelly and // then start scrolling) // message[i++] = ' '; // message[i++] = ' '; // message[i++] = ' '; // message[i++] = ' '; // enter message until 300 characters entered or <enter> key pressed while((ch != 13) || (i < 100)) { ch = getchar(); if (ch != 13) { if (ch == 8) { if (chcount == 0) { lcd_clear(); x = 0; i = 0; } else if (chcount>32) { y = 0; message[--i] = ' '; for (c=33;c>=2;c--) { goto_address(y);


display_char(message[chcount-c]); y++; } chcount--; x = chcount; --b; } else { message[--i] = ' '; goto_address(chcount-1); display_char(message[i]); goto_address(chcount-1); x--; chcount--; } } else if (chcount<32) { goto_address(x); message[i++] = ch; display_char(message[--i]); i++; x++; chcount++; } else { x = 0; b++; i = b; for (d=0;d<31;d++) { goto_address(x); display_char(message[i++]); x++; } goto_address(x); message[i++] = ch; display_char(message[--i]); i++; //delay_ms(10); chcount++; } }


// if q is pressed clear the LCD // (code only writes to the first LCD line so // if the line is longer than 16 chars i cant see the rest of the chars // , there will be a menu system in the future software version // and the line on the LCD will be scrolled // to the left automatically as the cursor gets to the end of the line //, for now use this dirty solution:)) if (ch == 13) { i = 0; message_matrix[i++] = ' '; message_matrix[i++] = ' '; message_matrix[i++] = ' '; message_matrix[i++] = ' '; for (j=0; j
} } // message[i++] = ' '; // message[i++] = ' '; // message[i++] = ' '; // message[i++] = ' '; } } void display_matrix(void) { unsigned char row, i, currentChar, charOffset, tmpCurrentChar, tmpCharOffset, ledArray[20], messageLength; flash unsigned char *tmpDataPtr, *dataPtr; unsigned int j; messageLength = last_address - 4;


charOffset = 0; currentChar = 0; dataPtr = &led_chars[message_matrix[0] - 0x20][0]; while (!kbhit()) { tmpDataPtr = dataPtr; tmpCharOffset = charOffset; tmpCurrentChar = currentChar; for (i = 0; i<=19 ; i++) { ledArray[i] = *tmpDataPtr++; if (++tmpCharOffset==0x06) { tmpCharOffset = 0; if (++tmpCurrentChar == messageLength) tmpCurrentChar = 0; tmpDataPtr = &led_chars[message_matrix[tmpCurrentChar] - 0x20][0]; } } if (++charOffset == 0x06) { charOffset = 0; if (++currentChar == messageLength) currentChar = 0; } dataPtr = &led_chars[message_matrix[currentChar] - 0x20][charOffset]; row = 0x02; for (j=0; j<SCROLL_DELAY; j++) { for (i=0; i<=19 ; i++) { PORTB.2 = (ledArray[i] & row) ? 1 : 0; PORTB.3 = 0; PORTB.4 = 1; PORTB.3 = 1; PORTB.4 = 0; } PORTA = row; row <<= 1; if (!row) row = 0x02; delay_us(800); PORTA = 0x00; } } }


// Program Utama void main(void) { unsigned char i; #asm("cli"); // inisialisasi port DDRA = 0xff; DDRB = 0xff; DDRC = 0xff; DDRD = 0xeb; sebagai input

// disable global interrupt

// PORTC sebagai output // PORTC sebagai output kecuali PIND.2 & PIND.4

PORTA = 0x00; PORTB = 0x00; PORTC = 0x00; PORTD = 0X00; // inisialisasi usart UCSRA=0x00; UCSRB=0xD8; UCSRC=0x86; UBRRH=0x00; UBRRL=0x47; // inisialisasi keyboard inpt = kb_buffer; outpt = kb_buffer; buffcnt = 0; bitcount = 11; // inisialisasi LCD lcd_init(); // inisialisasi register interupsi MCUCR = 0x02; // interrupsi pada INT0 dengan transisi turun (falling edge) GICR = 0x40; // interrupsi INT0 enable #asm("sei");

// enable global interrupt

// welcome message welcome_message(); while(1)


{ lcd_clear(); menu_display(); i = getchar(); if (i == '1') { lcd_clear(); input_mode(); } else if (i == '2') { displaying_message(); display_matrix(); } else wrong_option(); } }


Pustaka <matrix.h>

flash unsigned char led_chars[94][6] = { 0x00,0x00,0x00,0x00,0x00,0x00, // space 0x00,0x00,0xfa,0x00,0x00,0x00, // ! 0x00,0xe0,0x00,0xe0,0x00,0x00, // " 0x28,0xfe,0x28,0xfe,0x28,0x00, // # 0x24,0x54,0xfe,0x54,0x48,0x00, // $ 0xc4,0xc8,0x10,0x26,0x46,0x00, // % 0x6c,0x92,0xaa,0x44,0x0a,0x00, // & 0x00,0xa0,0xc0,0x00,0x00,0x00, // ' 0x00,0x38,0x44,0x82,0x00,0x00, // ( 0x00,0x82,0x44,0x38,0x00,0x00, // ) 0x28,0x10,0x7c,0x10,0x28,0x00, // * 0x10,0x10,0x7c,0x10,0x10,0x00, // + 0x00,0x0a,0x0c,0x00,0x00,0x00, // , 0x10,0x10,0x10,0x10,0x10,0x00, // 0x00,0x06,0x06,0x00,0x00,0x00, // . 0x04,0x08,0x10,0x20,0x40,0x00, // / 0x7c,0x8a,0x92,0xa2,0x7c,0x00, // 0 0x00,0x42,0xfe,0x02,0x00,0x00, // 1 0x42,0x86,0x8a,0x92,0x62,0x00, // 2 0x84,0x82,0xa2,0xd2,0x8c,0x00, // 3 0x18,0x28,0x48,0xfe,0x08,0x00, // 4 0xe5,0xa2,0xa2,0xa2,0x9c,0x00, // 5 0x3c,0x52,0x92,0x92,0x0c,0x00, // 6 0x80,0x8e,0x90,0xa0,0xc0,0x00, // 7 0x6c,0x92,0x92,0x92,0x6c,0x00, // 8 0x60,0x92,0x92,0x94,0x78,0x00, // 9 0x00,0x6c,0x6c,0x00,0x00,0x00, // : 0x00,0x6a,0x6c,0x00,0x00,0x00, // ; 0x10,0x28,0x44,0x82,0x00,0x00, // < 0x28,0x28,0x28,0x28,0x28,0x00, // = 0x00,0x82,0x44,0x28,0x10,0x00, // > 0x40,0x80,0x8a,0x90,0x60,0x00, // ? 0x4c,0x92,0x9e,0x82,0x7c,0x00, // @ 0x7e,0x88,0x88,0x88,0x7e,0x00, // A 0xfe,0x92,0x92,0x92,0x6c,0x00, // B 0x7c,0x82,0x82,0x82,0x44,0x00, // C 0xfe,0x82,0x82,0x44,0x38,0x00, // D 0xfe,0x92,0x92,0x92,0x82,0x00, // E


0xfe,0x90,0x90,0x90,0x80,0x00, 0x7c,0x82,0x92,0x92,0x5e,0x00, 0xfe,0x10,0x10,0x10,0xfe,0x00, 0x00,0x82,0xfe,0x82,0x00,0x00, 0x04,0x02,0x82,0xfc,0x80,0x00, 0xfe,0x10,0x28,0x44,0x82,0x00, 0xfe,0x02,0x02,0x02,0x02,0x00, 0xfe,0x40,0x30,0x40,0xfe,0x00, 0xfe,0x20,0x10,0x08,0xfe,0x00, 0x7c,0x82,0x82,0x82,0x7c,0x00, 0xfe,0x90,0x90,0x90,0x60,0x00, 0x7c,0x82,0x8a,0x84,0x7a,0x00, 0xfe,0x90,0x98,0x94,0x62,0x00, 0x62,0x92,0x92,0x92,0x8c,0x00, 0x80,0x80,0xfe,0x80,0x80,0x00, 0xfc,0x02,0x02,0x02,0xfc,0x00, 0xf8,0x04,0x02,0x04,0xf8,0x00, 0xfc,0x02,0x1c,0x02,0xfc,0x00, 0xc6,0x28,0x10,0x28,0xc6,0x00, 0xe0,0x10,0x0e,0x10,0xe0,0x00, 0x86,0x8b,0x92,0xa2,0xc2,0x00, 0x00,0xfe,0x82,0x82,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x82,0x82,0xfe,0x00,0x00, 0x20,0x40,0x80,0x40,0x20,0x00, 0x02,0x02,0x02,0x02,0x02,0x00, 0x00,0x80,0x40,0x20,0x00,0x00, 0x04,0x2a,0x2a,0x2a,0x1e,0x00, 0xfe,0x12,0x22,0x22,0x1c,0x00, 0x1c,0x22,0x22,0x22,0x04,0x00, 0x1c,0x22,0x22,0x12,0xfe,0x00, 0x1c,0x2a,0x2a,0x2a,0x18,0x00, 0x10,0x7e,0x90,0x80,0x40,0x00, 0x30,0x4a,0x4a,0x4a,0x7c,0x00, 0xfe,0x10,0x20,0x20,0x1e,0x00, 0x00,0x22,0xbe,0x02,0x00,0x00, 0x04,0x02,0x22,0xbc,0x00,0x00, 0xfe,0x08,0x14,0x22,0x00,0x00, 0x00,0x82,0xfe,0x02,0x00,0x00, 0x3e,0x20,0x18,0x20,0x1e,0x00, 0x3e,0x10,0x20,0x20,0x1e,0x00, 0x1c,0x22,0x22,0x22,0x1c,0x00, 0x3e,0x28,0x28,0x28,0x10,0x00, 0x10,0x28,0x28,0x18,0x3e,0x00, 0x3e,0x10,0x20,0x20,0x10,0x00, 0x12,0x2a,0x2a,0x2a,0x04,0x00, 0x20,0xfc,0x22,0x02,0x04,0x00, 0x3c,0x02,0x02,0x04,0x3e,0x00,

// F // G // H // I // J // K // L // M // N // O // P // Q // R // S // T // U // V // W // X // Y // Z // [ // *** do not remove this empty char *** // ] // ^ // _ // ` // a // b // c // d // e // f // g // h // i // j // k // l // m // n // o // p // q // r // s // t // u


0x38,0x04,0x02,0x04,0x38,0x00, 0x3c,0x02,0x0c,0x02,0x3c,0x00, 0x22,0x14,0x08,0x14,0x22,0x00, 0x30,0x0a,0x0a,0x0a,0x3c,0x00, 0x22,0x26,0x2a,0x32,0x22,0x00, 0x00,0x10,0x6c,0x82,0x00,0x00, 0x00,0x00,0xfe,0x00,0x00,0x00, 0x00,0x82,0x6c,0x10,0x00,0x00 };

// v // w // x // y // z // { // |


Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture

•

•

•

• • •

– 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories – 8K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – 512 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles – 512 Bytes Internal SRAM – Programming Lock for Software Security Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels for TQFP Package Only 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x for TQFP Package Only – Byte-oriented Two-wire Serial Interface – Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby I/O and Packages – 32 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad MLF Operating Voltages – 2.7 - 5.5V for ATmega8535L – 4.5 - 5.5V for ATmega8535 Speed Grades – 0 - 8 MHz for ATmega8535L – 0 - 16 MHz for ATmega8535

8-bit Microcontroller with 8K Bytes In-System Programmable Flash ATmega8535 ATmega8535L

Advance Information Summary

Rev. 2502CS–AVR–04/03

Note: This is a summary document. A complete document is available on our web site at www.atmel.com .


1

Pin Configurations

Figure 1. Pinout ATmega8535 (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP1) PD6

PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 PC4 PC3 PC2 PC1 (SDA) PC0 (SCL) PD7 (OC2)

PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 PC4

(MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2

6 5 4 3 2 1 44 43 42 41 40

33 32 31 30 29 28 27 26 25 24 23

1 2 3 4 5 6 7 8 9 10 11

7 8 9 10 11 12 13 14 15 16 17

39 38 37 36 35 34 33 32 31 30 29

PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 PC4

Disclaimer

2

PD3 PD4 PD5 PD6 PD7 VCC GND (SCL) PC0 (SDA) PC1 PC2 PC3 (INT1) (OC1B) (OC1A) (ICP1) (OC2)

(INT1) (OC1B) (OC1A) (ICP1) (OC2)

PD3 PD4 PD5 PD6 PD7 VCC GND (SCL) PC0 (SDA) PC1 PC2 PC3

12 13 14 15 16 17 18 19 20 21 22

(MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2

18 19 20 21 22 23 24 25 26 27 28

44 43 42 41 40 39 38 37 36 35 34

PB4 (SS) PB3 (AIN1/OC0) PB2 (AIN0/INT2) PB1 (T1) PB0 (XCK/T0) GND VCC PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3)

PB4 (SS) PB3 (AIN1/OC0) PB2 (AIN0/INT2) PB1 (T1) PB0 (XCK/T0) GND VCC PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3)

PLCC

Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

ATmega8535(L) Papan informasi..., Evy Christian Sri Nugroho, FT UI, 2010

2502CS–AVR–04/03

ATmega8535(L) Overview

The ATmega8535 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the ATmega8535 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Block Diagram

Figure 2. Block Diagram PA0 - PA7

PC0 - PC7

PORTA DRIVERS/BUFFERS

PORTC DRIVERS/BUFFERS

PORTA DIGITAL INTERFACE

PORTC DIGITAL INTERFACE

VCC

GND

AVCC ADC INTERFACE

MUX & ADC

TWI

AREF PROGRAM COUNTER

STACK POINTER

PROGRAM FLASH

SRAM

TIMERS/ COUNTERS

OSCILLATOR

INTERNAL OSCILLATOR XTAL1

INSTRUCTION REGISTER

GENERAL PURPOSE REGISTERS

WATCHDOG TIMER

OSCILLATOR

XTAL2

X INSTRUCTION DECODER

Y

MCU CTRL. & TIMING

RESET

Z

CONTROL LINES

ALU

AVR CPU

STATUS REGISTER

EEPROM

PROGRAMMING LOGIC

SPI

USART

+ -

INTERNAL CALIBRATED OSCILLATOR

INTERRUPT UNIT

COMP. INTERFACE

PORTB DIGITAL INTERFACE

PORTD DIGITAL INTERFACE

PORTB DRIVERS/BUFFERS

PORTD DRIVERS/BUFFERS

PB0 - PB7

PD0 - PD7

3 2502CS–AVR–04/03


AVR313: Interfacing the PC AT Keyboard Features • • • •

Interfacing Standard PC AT Keyboards Requires Only Two I/O Pins. One of them must be an External Interrupt Pin No Extra Hardware Required Complete Example in C, Implementing a Keyboard to Serial Converter

Introduction Most microcontrollers requires some kind of a human interface. This application note describes one way of doing this using a standard PC AT keyboard.

8-bit Microcontroller Application Note

The Physical Interface The physical interface between the keyboard and the host is shown in Figure 1. Two signal lines are used, clock and data. The signal lines are open connector, with pullup resistors located in the keyboard. This allows either the keyboard or the host system to force a line to low level. Two connector types are available, the 5-pin DIN connector of “5D” type, and the smaller six-pin mini-DIN. The pin assignments are shown in Table 1. Figure 1. The Interface. Vcc

AVR VCC

+5V

INT0 (or INT1)

Clock

Pxy

Data

GND

Keyboard

GND

Rev. 1235B–AVR–05/02

1


Table 1. AT Keyboard Connector Pin Assignments 4 1

2

5 3

6 4

5 3

2

1

AT Computer

Timing

Signals

DIN41524, Female at Computer, 5-pin DIN 180o

6-pin Mini DIN PS2 Style Female at Computer

Clock

1

5

Data

2

1

nc

3

2,6

GND

4

3

+5V

5

4

Shield

Shell

Shell

The timing for the data transferred from the keyboard to the host is shown in Figure 2. The protocol is: one start bit (always 0), eight data bits, one odd parity bit and one stop bit (always 1). The data is valid during the low period of the clock pulse. The keyboard is generating the clock signal, and the clock pulses are typically 30-50 µs low and 30-50 µs high. The host system can send commands to the keyboard by forcing the clock line low. It then pulls the data line low (the start bit). Now, the clock line must be released. The keyboard will count 10 clock pulses. The data line must be set up to the right level by the host before the trailing edge of the clock pulse. After the tenth bit, the keyboard checks for a high level on the data line (the stop bit), and if it is high, it forces it low. This tells the host that the data is received by the keyboard. The software in this design note will not send any commands to the keyboard.

Scan Codes

The AT keyboard has a scan code associated with each key. When a key is pressed, this code is transmitted. If a key is held down for a while, it starts repeating. The repeat rate is typically 10 per second. When a key is released, a “break” code ($F0) is transmitted followed by the key scan code. For most of the keys, the scan code is one byte. Some keys like the Home, Insert and Delete keys have an extended scan code, from two to five bytes. The first byte is always $E0. This is also true for the “break” sequence, e.g., E0 F0 xx… AT keyboards are capable of handling three sets of scan codes, where set two is default. This example will only use set two.

The Software

The code supplied with this application note is a simple keyboard to RS-232 interface. The scan codes received from the keyboard are translated into appropriate ASCII characters and transmitted by the UART. The source code is written in C, and is easily modified and adaptable to all AVR microconrollers with SRAM. Note:

2

The linkerfile (AVR313.xcl) included in the software archive has to be included instead of the standard linkerfile. This is done from the include menu under XLINK – Options. The linker file applies to AT90S8515 only.

AVR313 Papan informasi..., Evy Christian Sri Nugroho, FT UI, 2010

1235B–AVR–05/02

AVR313 The Algorithm

Keyboard reception is handled by the interrupt function INT0_interrupt. The reception will operate independent of the rest of the program. The algorithm is quite simple: Store the value of the data line at the leading edge of the clock pulse. This is easily handled if the clock line is connected to the INT0 or INT1 pin. The interrupt function will be executed at every edge of the clock cycle, and data will be stored at the falling edge. After all bits are received, the data can be decoded. This is done by calling the decode function. For character keys, this function will store an ASCII character in a buffer. It will take into account if the shift key is held down when a key is pressed. Other keys like function keys, navigation keys (arrow keys, page up/down keys etc.) and modifier keys like Ctrl and Alt are ignored. The mapping from scan codes to ascii characters are handled with table look-ups, one table for shifted characters and one for un-shifted.

Modifications and Improvements

If the host falls out of sync with the keyboard, all subsequent data received will be wrong. One way to solve this is to use a time out. If 11 bits are not received within 1.5 ms, some error have occurred. The bit counter should be reset and the faulty data discarded. If keyboard parameters like typematic rate and delay are to be set, data must be sent to the keyboard. This can be done as described earlier. For the commands, see the keyboard manufacturer’s specifications. Figure 2. Timing for Keyboard to Host Transfer Clock Data

Main.c

Start

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Parity

Stop

#include #include <stdio.h> #include <stdlib.h> #include "io8515.h"

#include "serial.h" #include "gpr.h" #include "kb.h" void main(void) { unsigned char key; init_uart();

// Initializes the UART transmit buffer

init_kb();

// Initialize keyboard reception

while(1) { key=getchar(); putchar(key); delay(100); } }

3 1235B–AVR–05/02


Low_level_init.c

#include #include

int __low_level_init(void) { UBRR = 12;

// 19200bps @ 4 MHz

UCR

// TX enable

= 0x08;

GIMSK= 0x40;

// Enable INT0 interrupt

_SEI(); return 1; }

Serial.c

#include <stdio.h> #include #include

/* SFR declarations */

#include "serial.h" #define ESC 0x1b #define BUFF_SIZE 64

flash char CLR[] = {ESC, '[','H', ESC, '[', '2', 'J',0}; unsigned char UART_buffer[BUFF_SIZE]; unsigned char *inptr, *outptr; unsigned char buff_cnt;

void init_uart(void) { inptr =

UART_buffer;

outptr = UART_buffer; buff_cnt = 0; }

void clr(void) { puts_P(CLR); VT100 terminal

// Send a 'clear screen' to a

} int putchar(int c) { if (buff_cnt
// Put character into buffer

inptr++;

// Increment pointer

buff_cnt++;

if (inptr >= UART_buffer + BUFF_SIZE)

4

// Pointer wrapping


1235B–AVR–05/02

AVR313 inptr = UART_buffer;

UCR = 0x28;

// Enable UART Data register // empty interrupt

return 1; } else { return 0;

// Buffer is full

} } // Interrupt driven transmitter

interrupt [UART_UDRE_vect] void UART_UDRE_interrupt(void) { UDR = *outptr;

// Send next byte

outptr++;


if (outptr >= UART_buffer + BUFF_SIZE)

// Pointer wrapping

outptr = UART_buffer; if(--buff_cnt == 0)

// If buffer is empty:

UCR = UCR && (1<
//

disabled interrupt

}

Kb.c

#include #include "kb.h" #include "serial.h" #include "gpr.h" #include "scancodes.h"

#define BUFF_SIZE 64 unsigned char edge, bitcount;// 0 = neg.

1 = pos.

unsigned char kb_buffer[BUFF_SIZE]; unsigned char *inpt, *outpt; unsigned char buffcnt;

void init_kb(void) { inpt =

kb_buffer;// Initialize buffer

outpt = kb_buffer; buffcnt = 0; MCUCR = 2; // INT0 interrupt on falling edge

5 1235B–AVR–05/02


edge = 0;

// 0 = falling edge

1 = rising edge

bitcount = 11; } interrupt [INT0_vect] void INT0_interrupt(void) { static unsigned char data;// Holds the received scan code

if (!edge) // Routine entered at falling edge { if(bitcount < 11 && bitcount > 2)// Bit 3 to 10 is data. Parity bit, {

// start and stop bits are ignored. data = (data >> 1); if(PIND & 8) data = data | 0x80;// Store a '1'

} MCUCR = 3;// Set interrupt on rising edge edge = 1;

} else {

// Routine entered at rising edge

MCUCR = 2;// Set interrupt on falling edge edge = 0; if(--bitcount == 0)// All bits received { decode(data); bitcount = 11; } } }

void decode(unsigned char sc) { static unsigned char is_up=0, shift = 0, mode = 0; unsigned char i; if (!is_up)// Last data received was the up-key identifier { switch (sc) { case 0xF0 :// The up-key identifier is_up = 1; break; case 0x12 :// Left SHIFT shift = 1; break;

6


1235B–AVR–05/02

AVR313 case 0x59 :// Right SHIFT shift = 1; break; case 0x05 :// F1 if(mode == 0) mode = 1;// Enter scan code mode if(mode == 2) mode = 3;// Leave scan code mode break; default: if(mode == 0 || mode == 3)// If ASCII mode { if(!shift)// If shift not pressed, {

// do a table look-up for(i = 0; unshifted[i][0]!=sc && unshifted[i][0]; i++); if (unshifted[i][0] == sc) { put_kbbuff(unshifted[i][1]); }

} else {// If shift pressed for(i = 0; shifted[i][0]!=sc && shifted[i][0]; i++); if (shifted[i][0] == sc) { put_kbbuff(shifted[i][1]); } } } else{ // Scan code mode print_hexbyte(sc);// Print scan code put_kbbuff(' '); put_kbbuff(' '); } break; } } else { is_up = 0;// Two 0xF0 in a row not allowed switch (sc) { case 0x12 :// Left SHIFT shift = 0; break; case 0x59 :// Right SHIFT shift = 0; break;

case 0x05 :// F1 if(mode == 1) mode = 2; if(mode == 3) mode = 0;

7 1235B–AVR–05/02


break; case 0x06 :// F2 clr(); break; } } }

void put_kbbuff(unsigned char c) { if (buffcnt

buffcnt++; if (inpt >= kb_buffer + BUFF_SIZE)// Pointer wrapping inpt = kb_buffer; } } int getchar(void) { int byte; while(buffcnt == 0);// Wait for data

byte = *outpt;// Get byte outpt++;


if (outpt >= kb_buffer + BUFF_SIZE)// Pointer wrapping outpt = kb_buffer;

buffcnt--; // Decrement buffer count return byte; }

8


1235B–AVR–05/02

AVR313 Gpr.c

#include "gpr.h"

void print_hexbyte(unsigned char i) { unsigned char h, l; h = i & 0xF0;

// High nibble

h = h>>4; h = h + '0'; if (h > '9') h = h + 7; l = (i & 0x0F)+'0';

// Low nibble

if (l > '9') l = l + 7;

putchar(h); putchar(l); }

void delay(char d) { char i,j,k; for(i=0; i
Pindefs.h

//********************* // Pin definition file //*********************

// Keyboard konnections #define PIN_KB

PIND

#define PORT_KB PORTD #define CLOCK

2

#define DATAPIN 3

9 1235B–AVR–05/02


Scancodes.h

// Unshifted characters flash unsigned char unshifted[][2] = { 0x0d,9, 0x0e,'|', 0x15,'q', 0x16,'1', 0x1a,'z', 0x1b,'s', 0x1c,'a', 0x1d,'w', 0x1e,'2', 0x21,'c', 0x22,'x', 0x23,'d', 0x24,'e', 0x25,'4', 0x26,'3', 0x29,' ', 0x2a,'v', 0x2b,'f', 0x2c,'t', 0x2d,'r', 0x2e,'5', 0x31,'n', 0x32,'b', 0x33,'h', 0x34,'g', 0x35,'y', 0x36,'6', 0x39,',', 0x3a,'m', 0x3b,'j', 0x3c,'u', 0x3d,'7', 0x3e,'8', 0x41,',', 0x42,'k', 0x43,'i', 0x44,'o', 0x45,'0', 0x46,'9', 0x49,'.', 0x4a,'-', 0x4b,'l', 0x4c,'ø', 0x4d,'p', 0x4e,'+', 0x52,'æ', 0x54,'å', 0x55,'\\',

10


1235B–AVR–05/02

AVR313 0x5a,13, 0x5b,'¨', 0x5d,'\'', 0x61,'<', 0x66,8, 0x69,'1', 0x6b,'4', 0x6c,'7', 0x70,'0', 0x71,',', 0x72,'2', 0x73,'5', 0x74,'6', 0x75,'8', 0x79,'+', 0x7a,'3', 0x7b,'-', 0x7c,'*', 0x7d,'9', 0,0 }; // Shifted characters flash unsigned char shifted[][2] = { 0x0d,9, 0x0e,'§', 0x15,'Q', 0x16,'!', 0x1a,'Z', 0x1b,'S', 0x1c,'A', 0x1d,'W', 0x1e,'"', 0x21,'C', 0x22,'X', 0x23,'D', 0x24,'E', 0x25,'¤', 0x26,'#', 0x29,' ', 0x2a,'V', 0x2b,'F', 0x2c,'T', 0x2d,'R', 0x2e,'%', 0x31,'N', 0x32,'B', 0x33,'H', 0x34,'G', 0x35,'Y', 0x36,'&',

11 1235B–AVR–05/02


0x39,'L', 0x3a,'M', 0x3b,'J', 0x3c,'U', 0x3d,'/', 0x3e,'(', 0x41,';', 0x42,'K', 0x43,'I', 0x44,'O', 0x45,'=', 0x46,')', 0x49,':', 0x4a,'_', 0x4b,'L', 0x4c,'Ø', 0x4d,'P', 0x4e,'?', 0x52,'Æ', 0x54,'Å', 0x55,'`', 0x5a,13, 0x5b,'^', 0x5d,'*', 0x61,'>', 0x66,8, 0x69,'1', 0x6b,'4', 0x6c,'7', 0x70,'0', 0x71,',', 0x72,'2', 0x73,'5', 0x74,'6', 0x75,'8', 0x79,'+', 0x7a,'3', 0x7b,'-', 0x7c,'*', 0x7d,'9', 0,0 };

12


1235B–AVR–05/02

Atmel Headquarters

Atmel Operations

Corporate Headquarters

Memory

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Printed on recycled paper. 1235B–AVR–05/02


0M

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega8535 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain in TQFP package, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the asynchronous timer continue to run. The device is manufactured using Atmel’s high density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8535 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega8535 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, InCircuit Emulators, and evaluation kits.

AT90S8535 Compatibility The ATmega8535 provides all the features of the AT90S8535. In addition, several new features are added. The ATmega8535 is backward compatible with AT90S8535 in most cases. However, some incompatibilities between the two microcontrollers exist. To solve this problem, an AT90S8535 compatibility mode can be selected by programming the S8535C fuse. ATmega8535 is pin compatible with AT90S8535, and can replace the AT90S8535 on current Printed Circuit Boards. However, the location of fuse bits and the electrical characteristics differs between the two devices. AT90S8535 Compatibility Mode

4

Programming the S8535C fuse will change the following functionality: •

The timed sequence for changing the Watchdog Time-out period is disabled. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 43 for details.

•

The double buffering of the USART Receive Register is disabled. See “AVR USART vs. AVR UART – Compatibility” on page 142 for details.


2502CS–AVR–04/03

ATmega8535(L) Pin Descriptions VCC

Digital supply voltage.

GND

Ground.

Port A (PA7..PA0)

Port A serves as the analog inputs to the A/D Converter. Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega8535 as listed on page 57.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega8535 as listed on page 61.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 35. Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting Oscillator amplifier.

AVCC

AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.

AREF

AREF is the analog reference pin for the A/D Converter.

5 2502CS–AVR–04/03


.

Register Summary Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x3F (0x5F)

SREG

I

T

H

S

V

N

Z

C

8

0x3E (0x5E)

SPH

–

–

–

–

–

SP10

SP9

SP8

10

0x3D (0x5D)

SPL

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

10

0x3C (0x5C)

OCR0

0x3B (0x5B)

GICR

–

IVSEL

IVCE

47, 66

INT1

INT0

INT2

–

82

–

0x3A (0x5A)

GIFR

INTF1

INTF0

INTF2

–

–

–

–

–

67

0x39 (0x59)

TIMSK

OCIE2

TOIE2

TICIE1

OCIE1A

OCIE1B

TOIE1

OCIE0

TOIE0

82, 112, 130

0x38 (0x58)

TIFR

OCF2

TOV2

ICF1

OCF1A

OCF1B

TOV1

OCF0

TOV0

83, 113, 131

0x37 (0x57)

SPMCR

SPMIE

RWWSB

–

RWWSRE

BLBSET

PGWRT

PGERS

SPMEN

224

0x36 (0x56)

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

177

0x35 (0x55)

MCUCR

SM2

SE

SM1

SM0

ISC11

ISC10

ISC01

ISC00

30, 65

0x34 (0x54)

MCUCSR

–

ISC2

–

–

WDRF

BORF

EXTRF

PORF

38, 66

0x33 (0x53)

TCCR0

FOC0

WGM00

COM01

COM00

WGM01

CS02

CS01

CS00

0x32 (0x52)

TCNT0

0x31 (0x51)

OSCCAL

0x30 (0x50)

SFIOR

ADTS2

ADTS1

ADTS0

–

Timer/Counter0 (8 Bits)

80 82

Oscillator Calibration Register

28

ACME

PUD

PSR2

PSR10

56,85,132,199,219

0x2F (0x4F)

TCCR1A

COM1A1

COM1A0

COM1B1

COM1B0

FOC1A

FOC1B

WGM11

WGM10

107

0x2E (0x4E)

TCCR1B

ICNC1

ICES1

–

WGM13

WGM12

CS12

CS11

CS10

110

0x2D (0x4D)

TCNT1H

Timer/Counter1 – Counter Register High Byte

111

0x2C (0x4C)

TCNT1L

111

0x2B (0x4B)

OCR1AH

Timer/Counter1 – Counter Register Low Byte Timer/Counter1 – Output Compare Register A High Byte

0x2A (0x4A)

OCR1AL

Timer/Counter1 – Output Compare Register A Low Byte

111

0x29 (0x49)

OCR1BH

Timer/Counter1 – Output Compare Register B High Byte

111 111

111

0x28 (0x48)

OCR1BL

Timer/Counter1 – Output Compare Register B Low Byte

0x27 (0x47)

ICR1H

Timer/Counter1 – Input Capture Register High Byte

111

0x26 (0x46)

ICR1L

Timer/Counter1 – Input Capture Register Low Byte

111

0x25 (0x45)

TCCR2

0x24 (0x44)

TCNT2

FOC2

WGM20

COM21

COM20

WGM21

CS22

CS21

CS20

Timer/Counter2 (8 Bits) Timer/Counter2 Output Compare Register

125 127

0x23 (0x43)

OCR2

0x22 (0x42)

ASSR

–

–

–

–

AS2

TCN2UB

OCR2UB

TCR2UB

0x21 (0x41)

WDTCR

–

–

–

WDCE

WDE

WDP2

WDP1

WDP0

UBRRH

URSEL

–

–

–

0x20(1) (0x40)(1)

6

Timer/Counter0 Output Compare Register

Page

128

UBRR[11:8]

128 40 165

UCSRC

URSEL

UMSEL

UPM1

UPM0

USBS

UCSZ1

UCSZ0

UCPOL

0x1F (0x3F)

EEARH

–

–

–

–

–

–

–

EEAR8

0x1E (0x3E)

EEARL

EEPROM Address Register Low Byte

163 17 17

0x1D (0x3D)

EEDR

0x1C (0x3C)

EECR

–

–

–

EEPROM Data Register –

EERIE

EEMWE

EEWE

EERE

17

17

0x1B (0x3B)

PORTA

PORTA7

PORTA6

PORTA5

PORTA4

PORTA3

PORTA2

PORTA1

PORTA0

63

0x1A (0x3A)

DDRA

DDA7

DDA6

DDA5

DDA4

DDA3

DDA2

DDA1

DDA0

63

0x19 (0x39)

PINA

PINA7

PINA6

PINA5

PINA4

PINA3

PINA2

PINA1

PINA0

63

0x18 (0x38)

PORTB

PORTB7

PORTB6

PORTB5

PORTB4

PORTB3

PORTB2

PORTB1

PORTB0

63

0x17 (0x37)

DDRB

DDB7

DDB6

DDB5

DDB4

DDB3

DDB2

DDB1

DDB0

63

0x16 (0x36)

PINB

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

64

0x15 (0x35)

PORTC

PORTC7

PORTC6

PORTC5

PORTC4

PORTC3

PORTC2

PORTC1

PORTC0

64

0x14 (0x34)

DDRC

DDC7

DDC6

DDC5

DDC4

DDC3

DDC2

DDC1

DDC0

64

0x13 (0x33)

PINC

PINC7

PINC6

PINC5

PINC4

PINC3

PINC2

PINC1

PINC0

64

0x12 (0x32)

PORTD

PORTD7

PORTD6

PORTD5

PORTD4

PORTD3

PORTD2

PORTD1

PORTD0

64

0x11 (0x31)

DDRD

DDD7

DDD6

DDD5

DDD4

DDD3

DDD2

DDD1

DDD0

64

0x10 (0x30)

PIND

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

0x0F (0x2F)

SPDR

SPI Data Register

64 139

0x0E (0x2E)

SPSR

SPIF

WCOL

–

–

–

–

–

SPI2X

0x0D (0x2D)

SPCR

SPIE

SPE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

0x0C (0x2C)

UDR

USART I/O Data Register

139 137 160

0x0B (0x2B)

UCSRA

RXC

TXC

UDRE

FE

DOR

PE

U2X

MPCM

0x0A (0x2A)

UCSRB

RXCIE

TXCIE

UDRIE

RXEN

TXEN

UCSZ2

RXB8

TXB8

0x09 (0x29)

UBRRL

USART Baud Rate Register Low Byte

161 162 165

0x08 (0x28)

ACSR

ACD

ACBG

ACO

ACI

ACIE

ACIC

ACIS1

ACIS0

199

0x07 (0x27)

ADMUX

REFS1

REFS0

ADLAR

MUX4

MUX3

MUX2

MUX1

MUX0

215

0x06 (0x26)

ADCSRA

ADEN

ADSC

ADATE

ADIF

ADIE

ADPS2

ADPS1

ADPS0

217

0x05 (0x25)

ADCH

ADC Data Register High Byte

218

0x04 (0x24)

ADCL

ADC Data Register Low Byte

218

0x03 (0x23)

TWDR

0x02 (0x22)

TWAR

TWA6

TWA5

TWA4

Two-wire Serial Interface Data Register TWA3

TWA2

TWA1

TWA0

TWGCE

179 180

0x01 (0x21)

TWSR

TWS7

TWS6

TWS5

TWS4

TWS3

–

TWPS1

TWPS0

179


2502CS–AVR–04/03

ATmega8535(L) Register Summary (Continued) Address

Name

0x00 (0x20)

TWBR

Notes:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Two-wire Serial Interface Bit Rate Register

Bit 0

Page 177

1. Refer to the USART description for details on how to access UBRRH and UCSRC. 2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

7 2502CS–AVR–04/03


Instruction Set Summary Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS ADD

Rd, Rr

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

1

ADC

Rd, Rr

Add with Carry two Registers

Rd ← Rd + Rr + C

Z,C,N,V,H

1

ADIW

Rdl,K

Add Immediate to Word

Rdh:Rdl ← Rdh:Rdl + K

Z,C,N,V,S

2

SUB

Rd, Rr

Subtract two Registers

Rd ← Rd - Rr

Z,C,N,V,H

1

SUBI

Rd, K

Subtract Constant from Register

Rd ← Rd - K

Z,C,N,V,H

1

SBC

Rd, Rr

Subtract with Carry two Registers

Rd ← Rd - Rr - C

Z,C,N,V,H

1

SBCI

Rd, K

Subtract with Carry Constant from Reg.

Rd ← Rd - K - C

Z,C,N,V,H

1

SBIW

Rdl,K

Subtract Immediate from Word

Rdh:Rdl ← Rdh:Rdl - K

Z,C,N,V,S

2 1

AND

Rd, Rr

Logical AND Registers

Rd ← Rd • Rr

Z,N,V

ANDI

Rd, K

Logical AND Register and Constant

Rd ← Rd • K

Z,N,V

1

OR

Rd, Rr

Logical OR Registers

Rd ← Rd v Rr

Z,N,V

1

ORI

Rd, K

Logical OR Register and Constant

Rd ← Rd v K

Z,N,V

1

EOR

Rd, Rr

Exclusive OR Registers

Rd ← Rd ⊕ Rr

Z,N,V

1

COM

Rd

One’s Complement

Rd ← 0xFF − Rd

Z,C,N,V

1

NEG

Rd

Two’s Complement

Rd ← 0x00 − Rd

Z,C,N,V,H

1

SBR

Rd,K

Set Bit(s) in Register

Rd ← Rd v K

Z,N,V

1

CBR

Rd,K

Clear Bit(s) in Register

Rd ← Rd • (0xFF - K)

Z,N,V

1

INC

Rd

Increment

Rd ← Rd + 1

Z,N,V

1

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

1

TST

Rd

Test for Zero or Minus

Rd ← Rd • Rd

Z,N,V

1

CLR

Rd

Clear Register

Rd ← Rd ⊕ Rd

Z,N,V

1

SER

Rd

Set Register

Rd ← 0xFF

None

1

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

Z,C

2

MULS

Rd, Rr

Multiply Signed

R1:R0 ← Rd x Rr

Z,C

2

MULSU

Rd, Rr

Multiply Signed with Unsigned

R1:R0 ← Rd x Rr

Z,C

2

FMUL

Rd, Rr

Fractional Multiply Unsigned

R1:R0 ← (Rd x Rr) <<

Z,C

2

FMULS

Rd, Rr

Fractional Multiply Signed

Z,C

2

FMULSU

Rd, Rr

Fractional Multiply Signed with Unsigned

1 R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1

Z,C

2

BRANCH INSTRUCTIONS RJMP

k

IJMP

Relative Jump

PC ← PC + k + 1

None

2

Indirect Jump to (Z)

PC ← Z

None

2 3

JMP

k

Direct Jump

PC ← k

None

RCALL

k

Relative Subroutine Call

PC ← PC + k + 1

None

3

Indirect Call to (Z)

PC ← Z

None

3

ICALL

Direct Subroutine Call

PC ← k

None

4

RET

Subroutine Return

PC ← STACK

None

4

RETI

Interrupt Return

PC ← STACK

I None

CALL

k

4

CPSE

Rd,Rr

Compare, Skip if Equal

if (Rd = Rr) PC ← PC + 2 or 3

CP

Rd,Rr

Compare

Rd − Rr

Z, N,V,C,H

1

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

Z, N,V,C,H

1

CPI

Rd,K

Compare Register with Immediate

Rd − K

Z, N,V,C,H

SBRC

Rr, b

Skip if Bit in Register Cleared

if (Rr(b)=0) PC ← PC + 2 or 3

None

1/2/3

1 1/2/3

SBRS

Rr, b

Skip if Bit in Register is Set

if (Rr(b)=1) PC ← PC + 2 or 3

None

1/2/3

SBIC

P, b

Skip if Bit in I/O Register Cleared

if (P(b)=0) PC ← PC + 2 or 3

None

1/2/3

SBIS

P, b

Skip if Bit in I/O Register is Set

if (P(b)=1) PC ← PC + 2 or 3

None

1/2/3

BRBS

s, k

Branch if Status Flag Set

if (SREG(s) = 1) then PC←PC+k + 1

None

1/2

BRBC

s, k

Branch if Status Flag Cleared

if (SREG(s) = 0) then PC←PC+k + 1

None

1/2

BREQ

k

Branch if Equal

if (Z = 1) then PC ← PC + k + 1

None

1/2

BRNE

k

Branch if Not Equal

if (Z = 0) then PC ← PC + k + 1

None

1/2

BRCS

k

Branch if Carry Set

if (C = 1) then PC ← PC + k + 1

None

1/2

BRCC

k

Branch if Carry Cleared

if (C = 0) then PC ← PC + k + 1

None

1/2

BRSH

k

Branch if Same or Higher

if (C = 0) then PC ← PC + k + 1

None

1/2

BRLO

k

Branch if Lower

if (C = 1) then PC ← PC + k + 1

None

1/2

BRMI

k

Branch if Minus

if (N = 1) then PC ← PC + k + 1

None

1/2

BRPL

k

Branch if Plus

if (N = 0) then PC ← PC + k + 1

None

1/2

BRGE

k

Branch if Greater or Equal, Signed

if (N ⊕ V= 0) then PC ← PC + k + 1

None

1/2

BRLT

k

Branch if Less Than Zero, Signed

if (N ⊕ V= 1) then PC ← PC + k + 1

None

1/2

BRHS

k

Branch if Half Carry Flag Set

if (H = 1) then PC ← PC + k + 1

None

1/2

BRHC

k

Branch if Half Carry Flag Cleared

if (H = 0) then PC ← PC + k + 1

None

1/2

BRTS

k

Branch if T Flag Set

if (T = 1) then PC ← PC + k + 1

None

1/2

BRTC

k

Branch if T Flag Cleared

if (T = 0) then PC ← PC + k + 1

None

1/2

BRVS

k

Branch if Overflow Flag is Set

if (V = 1) then PC ← PC + k + 1

None

1/2

BRVC

k

Branch if Overflow Flag is Cleared

if (V = 0) then PC ← PC + k + 1

None

1/2

BRIE

k

Branch if Interrupt Enabled

if ( I = 1) then PC ← PC + k + 1

None

1/2

8


2502CS–AVR–04/03

ATmega8535(L) Mnemonics

Operands

Description

Operation

Flags

BRID

k

Branch if Interrupt Disabled

if ( I = 0) then PC ← PC + k + 1

None

#Clocks 1/2

DATA TRANSFER INSTRUCTIONS MOV

Rd, Rr

Move Between Registers

1

Rd, Rr

Copy Register Word

Rd ← Rr Rd+1:Rd ← Rr+1:Rr

None

MOVW

None

1

LDI

Rd, K

Load Immediate

Rd ← K

None

1

LD

Rd, X

Load Indirect

Rd ← (X)

None

2

LD

Rd, X+

Load Indirect and Post-Inc.

Rd ← (X), X ← X + 1

None

2

LD

Rd, - X

Load Indirect and Pre-Dec.

X ← X - 1, Rd ← (X)

None

2

LD

Rd, Y

Load Indirect

Rd ← (Y)

None

2

LD

Rd, Y+


Rd ← (Y), Y ← Y + 1

None

2

LD

Rd, - Y


Y ← Y - 1, Rd ← (Y)

None

2

LDD

Rd,Y+q

Load Indirect with Displacement

Rd ← (Y + q)

None

2

LD

Rd, Z

Load Indirect

Rd ← (Z)

None

2

LD

Rd, Z+


Rd ← (Z), Z ← Z+1

None

2

LD

Rd, -Z


Z ← Z - 1, Rd ← (Z)

None

2

LDD

Rd, Z+q

Load Indirect with Displacement

Rd ← (Z + q)

None

2

LDS

Rd, k

Load Direct from SRAM

Rd ← (k)

None

2

ST

X, Rr

Store Indirect

(X) ← Rr

None

2

ST

X+, Rr

Store Indirect and Post-Inc.

(X) ← Rr, X ← X + 1

None

2

ST

- X, Rr

Store Indirect and Pre-Dec.

X ← X - 1, (X) ← Rr

None

2

ST

Y, Rr

Store Indirect

(Y) ← Rr

None

2

ST

Y+, Rr


(Y) ← Rr, Y ← Y + 1

None

2

ST

- Y, Rr


Y ← Y - 1, (Y) ← Rr

None

2

STD

Y+q,Rr

Store Indirect with Displacement

(Y + q) ← Rr

None

2

ST

Z, Rr

Store Indirect

(Z) ← Rr

None

2

ST

Z+, Rr


(Z) ← Rr, Z ← Z + 1

None

2

ST

-Z, Rr


Z ← Z - 1, (Z) ← Rr

None

2

STD

Z+q,Rr

Store Indirect with Displacement

(Z + q) ← Rr

None

2

STS

k, Rr

Store Direct to SRAM

(k) ← Rr

None

2

Load Program Memory

R0 ← (Z)

None

3

LPM LPM

Rd, Z

Load Program Memory

Rd ← (Z)

None

3

LPM

Rd, Z+

Load Program Memory and Post-Inc

Rd ← (Z), Z ← Z+1

None

3

Store Program Memory

(Z) ← R1:R0

None

-

In Port

Rd ← P

None

1 1

SPM IN

Rd, P

OUT

P, Rr

Out Port

P ← Rr

None

PUSH

Rr

Push Register on Stack

STACK ← Rr

None

2

POP

Rd

Pop Register from Stack

Rd ← STACK

None

2

BIT AND BIT-TEST INSTRUCTIONS SBI

P,b

Set Bit in I/O Register

I/O(P,b) ← 1

None

2

CBI

P,b

Clear Bit in I/O Register

I/O(P,b) ← 0

None

2

LSL

Rd

Logical Shift Left

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

1

LSR

Rd

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

1

ROL

Rd

Rotate Left Through Carry

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

1

ROR

Rd

Rotate Right Through Carry

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

1

ASR

Rd

Arithmetic Shift Right

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

1

SWAP

Rd

Swap Nibbles

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

1

BSET

s

Flag Set

SREG(s) ← 1

SREG(s)

1

BCLR

s

Flag Clear

SREG(s) ← 0

SREG(s)

1

BST

Rr, b

Bit Store from Register to T

T ← Rr(b)

T

1

BLD

Rd, b

Bit load from T to Register

Rd(b) ← T

None

1

SEC

Set Carry

C←1

C

1

CLC

Clear Carry

C←0

C

1

SEN

Set Negative Flag

N←1

N

1

CLN

Clear Negative Flag

N←0

N

1

SEZ

Set Zero Flag

Z←1

Z

1

CLZ

Clear Zero Flag

Z←0

Z

1

SEI

Global Interrupt Enable

I←1

I

1

CLI

Global Interrupt Disable

I←0

I

1

SES

Set Signed Test Flag

S←1

S

1

CLS

Clear Signed Test Flag

S←0

S

1

SEV

Set Twos Complement Overflow.

V←1

V

1

CLV

Clear Twos Complement Overflow

V←0

V

1

SET

Set T in SREG

T←1

T

1

CLT

Clear T in SREG

T←0

T

1

SEH

Set Half Carry Flag in SREG

H←1

H

1

CLH

Clear Half Carry Flag in SREG

H←0

H

1

9 2502CS–AVR–04/03


Mnemonics

Operands

Description

Operation

Flags

#Clocks

MCU CONTROL INSTRUCTIONS NOP

No Operation

None

1

SLEEP

Sleep

(see specific descr. for Sleep function)

None

1

WDR

Watchdog Reset

(see specific descr. for WDR/Timer)

None

1

BREAK

Break

For On-chip Debug Only

None

N/A

10


2502CS–AVR–04/03

ATmega8535(L) Ordering Information(1) Speed (MHz)

Power Supply

8

2.7 - 5.5V

16

Note:

4.5 - 5.5V

Ordering Code

Package

ATmega8535L-8AC ATmega8535L-8PC ATmega8535L-8JC ATmega8535L-8MC

44A 40P6 44J 44M1

Operation Range

ATmega8535L-8AI ATmega8535L-8PI ATmega8535L-8JI ATmega8535L-8MI

44A 40P6 44J 44M1

Industrial (-40°C to 85°C)

ATmega8535-16AC ATmega8535-16PC ATmega8535-16JC ATmega8535-16MC

44A 40P6 44J 44M1

Commercial

ATmega8535-16AI ATmega8535-16PI ATmega8535-16JI ATmega8535-16MI

44A 40P6 44J 44M1

Commercial (0°C to 70°C)

(0°C to 70°C)

Industrial (-40°C to 85°C)

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.

Package Type 44A

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40P6

40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44J

44-lead, Plastic J-ledded Chip Carrier (PLCC)

44M1-A

44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Micro Lead Frame Package (MLF)

11 2502CS–AVR–04/03


Packaging Information 44A

PIN 1 B PIN 1 IDENTIFIER

E1

e

E

D1 D C

0˚~7˚ A1

A2

A

L COMMON DIMENSIONS (Unit of Measure = mm)

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.

SYMBOL

MIN

NOM

MAX

A

–

–

1.20

A1

0.05

–

0.15

A2

0.95

1.00

1.05

D

11.75

12.00

12.25

D1

9.90

10.00

10.10

E

11.75

12.00

12.25

E1

9.90

10.00

10.10

B

0.30

–

0.45

C

0.09

–

0.20

L

0.45

–

0.75

e

NOTE

Note 2

Note 2

0.80 TYP

10/5/2001

R

12

2325 Orchard Parkway San Jose, CA 95131

TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

DRAWING NO.

REV.

44A

B


2502CS–AVR–04/03

ATmega8535(L) 40P6

D

PIN 1

E1

A

SEATING PLANE

A1

L B

B1 e E

0º ~ 15º

C eB

Notes:

COMMON DIMENSIONS (Unit of Measure = mm)

REF

1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

SYMBOL

MIN

NOM

MAX

A

–

–

4.826

A1

0.381

–

–

D

52.070

–

52.578

E

15.240

–

15.875

E1

13.462

–

13.970

B

0.356

–

0.559

B1

1.041

–

1.651

L

3.048

–

3.556

C

0.203

–

0.381

eB

15.494

–

17.526

e

NOTE

Note 2

Note 2

2.540 TYP

09/28/01

R


TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP)

DRAWING NO. 40P6

REV. B

13 2502CS–AVR–04/03


44J

1.14(0.045) X 45˚

PIN NO. 1

1.14(0.045) X 45˚

0.318(0.0125) 0.191(0.0075)

IDENTIFIER

E1

D2/E2

B1

E

B

e A2

D1

A1

D A

0.51(0.020)MAX 45˚ MAX (3X)


Notes:

1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum.

SYMBOL

MIN

NOM

MAX

A

4.191

–

4.572

A1

2.286

–

3.048

A2

0.508

–

–

D

17.399

–

17.653

D1

16.510

–

16.662

E

17.399

–

17.653

E1

16.510

–

16.662

D2/E2

14.986

–

16.002

B

0.660

–

0.813

B1

0.330

–

0.533

e

NOTE

Note 2

Note 2

1.270 TYP

10/04/01

R

14


TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)

DRAWING NO.

REV.

44J

B


2502CS–AVR–04/03

ATmega8535(L) 44M1-A

D

Marked Pin# 1 ID

E

SEATING PLANE

A1

TOP VIEW

A3 A L

Pin #1 Corner

D2

SIDE VIEW


E2

SYMBOL

MIN

NOM

MAX

A

0.80

0.90

1.00

A1

–

0.02

0.05

A3 b

0.25 REF 0.18

D

e

b

D2

E2

5.00

Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-1.

0.30

5.20

5.40

7.00 BSC 5.00

e L

0.23 7.00 BSC

E

BOTTOM VIEW

NOTE

5.20

5.40

0.50 BSC 0.35

0.55

0.75

01/15/03

R


TITLE 44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm Micro Lead Frame Package (MLF)

DRAWING NO. 44M1

REV. C

15 2502CS–AVR–04/03


Data Sheet Change Log for ATmega8535

Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision.

Changes from Rev. 2502A-06/02 to Rev. 2502B-09/02

1. Canged the Endurance on the Flash to 10,000 Write/Erase Cycles.

Changes from Rev. 2502B-09/02 to Rev. 2502C-05/03

1. Updated “Packaging Information” on page 12. 2. Updated Figure 1 on page 2, Figure 84 on page 175, Figure 85 on page 181, Figure 87 on page 187, Figure 98 on page 203. 3. Added the section “EEPROM Write During Power-down Sleep Mode” on page 20. 4. Removed the references to the application notes “Multi-purpose Oscillator” and “32 kHz Crystal Oscillator”, which do not exist. 5. Updated code examples on page 42. 6. Removed ADHSM bit. 7. Renamed Port D pin ICP to ICP1. See “Alternate Functions of Port D” on page 61. 8. Added information about PWM symmetry for Timer 0 on page 76 and Timer 2 on page 123. 9. Updated Table 68 on page 165, Table 75 on page 186, Table 76 on page 189, Table 77 on page 192, Table 108 on page 249, Table 113 on page 256. 10. Updated description on “Bit 5 – TWSTA: TWI START Condition Bit” on page 178. 11. Updated the description in “Filling the Temporary Buffer (Page Loading)” and “Performing a Page Write” on page 227. 12. Removed the section description in “SPI Serial Programming Characteristics” on page 250. 13. Updated “Electrical Characteristics” on page 251. 14. Updated “ADC Characteristics – Preliminary Data” on page 258. 14. Updated “Register Summary” on page 6. 15. Various Timer 1 corrections. 16. Added WD_FUSE period in Table 108 on page 249.

16


2502CS–AVR–04/03

Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600

Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500

Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369

Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581

Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314

RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340

Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60

ASIC/ASSP/Smart Cards

1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80

Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743

e-mail [email protected]

Web Site http://www.atmel.com

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.

© Atmel Corporation 2003. All rights reserved. Atmel® and combinations thereof, AVR® are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.

Printed on recycled paper. 2502CS–AVR–04/03


0M

38mm (1.5 INCH) 8x8 DOT MATRIX DISPLAY Part Number: TC15-11YWA

Yellow

Features

Description

z 1.5 INCH MATRIX HEIGHT.

The Yellow source color devices are made with Gallium

z DOT SIZE 3.7mm.

Arsenide Phosphide on Gallium Phosphide Yellow Light

z LOW CURRENT OPERATION.

Emitting Diode.

z HIGH CONTRAST AND LIGHT OUTPUT. z COMPATIBLE WITH ASCII AND EBCDIC CODES. z STACKABLE HORIZONTALLY AND VERTICALLY. z COLUMN CATHODE AND COLUMN ANODE AVAILABLE. z EASY MOUNTING ON P.C. BOARDS OR SOCKETS. z MULTICOLOR AVAILABLE. z MECHANICALLY RUGGED. z STANDARD : GRAY FACE, WHITE DOT. z RoHS COMPLIANT.

Package Dimensions& Internal Circuit Diagram

Notes: 1. All dimensions are in millimeters (inches), Tolerance is ±0.25(0.01")unless otherwise noted. 2. Specifications are subject to change without notice.

SPEC NO: DSAD2449

REV NO: V.8

DATE: MAY/24/2007

APPROVED: WYNEC

CHECKED: Joe Lee

DRAWN: Y.L.LI


PAGE: 1 OF 4 ERP: 1332000546

Selection Guide Part No.

Dice

TC15-11YWA

Iv (ucd) [1] @ 10mA

Lens Type

Yellow (GaAsP/GaP)

WHITE DIFFUSED

Min.

Typ.

1900

8000

Description

Column Cathode

Note: 1. Luminous intensity/ luminous Flux: +/-15%.

Electrical / Optical Characteristics at TA=25°C Symbol

Parameter

Device

Typ.

λpeak

Peak Wavelength

Yellow

λD [1]

Dominant Wavelength

Δλ1/2

Max.

Units

Test Conditions

590

nm

IF=20mA

Yellow

588

nm

IF=20mA

Spectral Line Half-width

Yellow

35

nm

IF=20mA

C

Capacitance

Yellow

20

pF

VF=0V;f=1MHz

VF [2]

Forward Voltage

Yellow

2.1

2.5

V

IF=20mA

IR

Reverse Current

Yellow

10

uA

VR=5V

Notes: 1.Wavelength: +/-1nm. 2. Forward Voltage: +/-0.1V.

Absolute Maximum Ratings at TA=25°C Parameter

Yellow

Units

Power dissipation

75

mW

DC Forward Current

30

mA

Peak Forward Current [1]

140

mA

5

V

Reverse Voltage Operating / Storage Temperature Lead Solder Temperature[2]

-40°C To +85°C 260°C For 3-5 Seconds

Notes: 1. 1/10 Duty Cycle, 0.1ms Pulse Width. 2. 2mm below package base.

SPEC NO: DSAD2449

REV NO: V.8

DATE: MAY/24/2007

APPROVED: WYNEC

CHECKED: Joe Lee

DRAWN: Y.L.LI


PAGE: 2 OF 4 ERP: 1332000546

Yellow

TC15-11YWA

SPEC NO: DSAD2449

REV NO: V.8

DATE: MAY/24/2007

APPROVED: WYNEC

CHECKED: Joe Lee

DRAWN: Y.L.LI


PAGE: 3 OF 4 ERP: 1332000546

PACKING & LABEL SPECIFICATIONS

TC15-11YWA

SPEC NO: DSAD2449

REV NO: V.8

DATE: MAY/24/2007

APPROVED: WYNEC

CHECKED: Joe Lee

DRAWN: Y.L.LI


PAGE: 4 OF 4 ERP: 1332000546

HD44780U (LCD-II) (Dot Matrix Liquid Crystal Display Controller/Driver)

ADE-207-272(Z) '99.9 Rev. 0.0 Description The HD44780U dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the functions such as display RAM, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. A single HD44780U can display up to one 8-character line or two 8-character lines. The HD44780U has pin function compatibility with the HD44780S which allows the user to easily replace an LCD-II with an HD44780U. The HD44780U character generator ROM is extended to generate 208 5 × 8 dot character fonts and 32 5 × 10 dot character fonts for a total of 240 different character fonts. The low power supply (2.7V to 5.5V) of the HD44780U is suitable for any portable battery-driven product requiring low power dissipation.

Features • 5 × 8 and 5 × 10 dot matrix possible • Low power operation support:  2.7 to 5.5V • Wide range of liquid crystal display driver power  3.0 to 11V • Liquid crystal drive waveform  A (One line frequency AC waveform) • Correspond to high speed MPU bus interface  2 MHz (when VCC = 5V) • 4-bit or 8-bit MPU interface enabled • 80 × 8-bit display RAM (80 characters max.) • 9,920-bit character generator ROM for a total of 240 character fonts  208 character fonts (5 × 8 dot)  32 character fonts (5 × 10 dot)

Papan informasi..., Evy Christian Sri Nugroho, FT UI, 2010 1

HD44780U • 64 × 8-bit character generator RAM  8 character fonts (5 × 8 dot)  4 character fonts (5 × 10 dot) • 16-common × 40-segment liquid crystal display driver • Programmable duty cycles  1/8 for one line of 5 × 8 dots with cursor  1/11 for one line of 5 × 10 dots with cursor  1/16 for two lines of 5 × 8 dots with cursor • Wide range of instruction functions:  Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift • Pin function compatibility with HD44780S • Automatic reset circuit that initializes the controller/driver after power on • Internal oscillator with external resistors • Low power consumption

Ordering Information Type No.

Package

CGROM

HD44780UA00FS HCD44780UA00 HD44780UA00TF HD44780UA02FS HCD44780UA02 HD44780UA02TF

FP-80B Chip TFP-80F FP-80B Chip TFP-80F

Japanese standard font

HD44780UBxxFS HCD44780UBxx HD44780UBxxTF

FP-80B Chip TFP-80F

European standard font

Custom font

Note: xx: ROM code No.


HD44780U HD44780U Block Diagram OSC1 OSC2

M

Reset circuit ACL

Timing generator

CPG

8

RS R/W E

Instruction register (IR)

7

Input/ output buffer

8

16-bit shift register

Common signal driver

40-bit latch circuit

Segment signal driver

7

40-bit shift register

8

7

DB4 to DB7

D

Display data RAM (DDRAM) 80 × 8 bits

Instruction decoder

MPU interface

Address counter

DB0 to DB3

CL1 CL2

SEG1 to SEG40

7

Data register (DR)

8 40 8

8

LCD drive voltage selector

Busy flag

GND

COM1 to COM16

Character generator ROM (CGROM) 9,920 bits

Character generator RAM (CGRAM) 64 bytes 5

Cursor and blink controller

5

Parallel/serial converter and attribute circuit VCC V1

V2

V3

V4

V5


HD44780U

65

66

67

68

69

70

71

72

73

74

75

76

77

78

1

64

2

63

3

62

4

61

5

60

6

59

7

58

8

57

9

56

10

55

11

54

FP-80B (Top view)

12 13

53 52

40

39

38

SEG39 SEG40 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DB7 DB6 DB5 DB4 DB3 DB2

OSC2 V1 V2 V3 V4 V5 CL1 CL2 VCC M D RS R/W E DB0 DB1

37

41 36

42

24 35

43

23

34

44

22

33

45

21

32

46

20

31

47

19

30

48

18

29

49

17

28

50

16

27

51

15

26

14

25

SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC1

79

80

SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38

HD44780U Pin Arrangement (FP-80B)


HD44780U

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

1

60

2

59

3

58

4

57

5

56

6

55

7

54

8

53

9

52

TFP-80F (Top view)

10 11

51 50

40

39

38

37

36

35

34

33

32

31

30

41

29

42

20

28

43

19

27

44

18

26

45

17

25

46

16

24

47

15

23

48

14

22

49

13

21

12

COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DB7 DB6 DB5 DB4

GND OSC1 OSC2 V1 V2 V3 V4 V5 CL1 CL2 VCC M D RS R/W E DB0 DB1 DB2 DB3

SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1

79

80

SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40

HD44780U Pin Arrangement (TFP-80F)


HD44780U HD44780U Pad Arrangement Chip size:

4.90 × 4.90 mm2

Coordinate: Pad center (µm)

2

1

Origin:

Chip center

Pad size:

114 × 114 µm2

80

63

Y

Type code

HD44780U

23

42 X


HD44780U HCD44780U Pad Location Coordinates Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Function SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 GND OSC1 OSC2 V1 V2 V3 V4 V5 CL1 CL2 VCC M D RS R/W E DB0 DB1

Coordinate X (um) Y (um) –2100 2313 –2280 2313 –2313 2089 –2313 1833 –2313 1617 –2313 1401 –2313 1186 –2313 970 –2313 755 –2313 539 –2313 323 –2313 108 –2313 –108 –2313 –323 –2313 –539 –2313 –755 –2313 –970 –2313 –1186 –2313 –1401 –2313 –1617 –2313 –1833 –2313 –2073 –2280 –2290 –2080 –2290 –1749 –2290 –1550 –2290 –1268 –2290 –941 –2290 –623 –2290 –304 –2290 –48 –2290 142 –2290 309 –2290 475 –2290 665 –2290 832 –2290 1022 –2290 1204 –2290 1454 –2290 1684 –2290

Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Function DB2 DB3 DB4 DB5 DB6 DB7 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23

Coordinate X (um) Y (um) 2070 –2290 2260 –2290 2290 –2099 2290 –1883 2290 –1667 2290 –1452 2313 –1186 2313 –970 2313 –755 2313 –539 2313 –323 2313 –108 2313 108 2313 323 2313 539 2313 755 2313 970 2313 1186 2313 1401 2313 1617 2313 1833 2313 2095 2296 2313 2100 2313 1617 2313 1401 2313 1186 2313 970 2313 755 2313 539 2313 323 2313 108 2313 –108 2313 –323 2313 –539 2313 –755 2313 –970 2313 –1186 2313 –1401 2313 –1617 2313


HD44780U Pin Functions Signal

No. of Lines

I/O

Device Interfaced with

RS

1

I

MPU

Selects registers. 0: Instruction register (for write) Busy flag: address counter (for read) 1: Data register (for write and read)

R/W

1

I

MPU

Selects read or write. 0: Write 1: Read

E

1

I

MPU

Starts data read/write.

DB4 to DB7

4

I/O

MPU

Four high order bidirectional tristate data bus pins. Used for data transfer and receive between the MPU and the HD44780U. DB7 can be used as a busy flag.

DB0 to DB3

4

I/O

MPU

Four low order bidirectional tristate data bus pins. Used for data transfer and receive between the MPU and the HD44780U. These pins are not used during 4-bit operation.

CL1

1

O

Extension driver

Clock to latch serial data D sent to the extension driver

CL2

1

O

Extension driver

Clock to shift serial data D

M

1

O

Extension driver

Switch signal for converting the liquid crystal drive waveform to AC

D

1

O

Extension driver

Character pattern data corresponding to each segment signal

COM1 to COM16 16

O

LCD

Common signals that are not used are changed to non-selection waveforms. COM9 to COM16 are non-selection waveforms at 1/8 duty factor and COM12 to COM16 are non-selection waveforms at 1/11 duty factor.

SEG1 to SEG40 40

O

LCD

Segment signals

V1 to V5

5

—

Power supply

Power supply for LCD drive VCC –V5 = 11 V (max)

VCC, GND

2

—

Power supply

VCC: 2.7V to 5.5V, GND: 0V

OSC1, OSC2

2

—

Oscillation resistor clock

When crystal oscillation is performed, a resistor must be connected externally. When the pin input is an external clock, it must be input to OSC1.

Function


HD44780U Function Description Registers The HD44780U has two 8-bit registers, an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator RAM (CGRAM). The IR can only be written from the MPU. The DR temporarily stores data to be written into DDRAM or CGRAM and temporarily stores data to be read from DDRAM or CGRAM. Data written into the DR from the MPU is automatically written into DDRAM or CGRAM by an internal operation. The DR is also used for data storage when reading data from DDRAM or CGRAM. When address information is written into the IR, data is read and then stored into the DR from DDRAM or CGRAM by an internal operation. Data transfer between the MPU is then completed when the MPU reads the DR. After the read, data in DDRAM or CGRAM at the next address is sent to the DR for the next read from the MPU. By the register selector (RS) signal, these two registers can be selected (Table 1). Busy Flag (BF) When the busy flag is 1, the HD44780U is in the internal operation mode, and the next instruction will not be accepted. When RS = 0 and R/W = 1 (Table 1), the busy flag is output to DB7. The next instruction must be written after ensuring that the busy flag is 0. Address Counter (AC) The address counter (AC) assigns addresses to both DDRAM and CGRAM. When an address of an instruction is written into the IR, the address information is sent from the IR to the AC. Selection of either DDRAM or CGRAM is also determined concurrently by the instruction. After writing into (reading from) DDRAM or CGRAM, the AC is automatically incremented by 1 (decremented by 1). The AC contents are then output to DB0 to DB6 when RS = 0 and R/W = 1 (Table 1). Table 1

Register Selection

RS

R/W

Operation

0

0

IR write as an internal operation (display clear, etc.)

0

1

Read busy flag (DB7) and address counter (DB0 to DB6)

1

0

DR write as an internal operation (DR to DDRAM or CGRAM)

1

1

DR read as an internal operation (DDRAM or CGRAM to DR)


HD44780U Display Data RAM (DDRAM) Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80 × 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display. The DDRAM address (ADD ) is set in the address counter (AC) as hexadecimal. • 1-line display (N = 0) (Figure 2)  When there are fewer than 80 display characters, the display begins at the head position. For example, if using only the HD44780, 8 characters are displayed. See Figure 3. When the display shift operation is performed, the DDRAM address shifts. See Figure 3. High order bits

Low order bits

Example: DDRAM address 4E

AC (hexadecimal) AC6 AC5 AC4 AC3 AC2 AC1 AC0

1

0

0

1

1

Figure 1 DDRAM Address Display position (digit)

1

2

3

DDRAM 00 01 address (hexadecimal)

4

02

5

79

..................

03 04

4E 4F

Figure 2 1-Line Display Display position

1

2

3

4

5

6

7

8

DDRAM address

00 01 02 03 04 05 06 07

For shift left

01 02 03 04 05 06 07 08

For shift right 4F 00 01 02 03 04 05 06

Figure 3 1-Line by 8-Character Display Example


80

1

0

HD44780U • 2-line display (N = 1) (Figure 4)  Case 1: When the number of display characters is less than 40 × 2 lines, the two lines are displayed from the head. Note that the first line end address and the second line start address are not consecutive. For example, when just the HD44780 is used, 8 characters × 2 lines are displayed. See Figure 5. When display shift operation is performed, the DDRAM address shifts. See Figure 5. Display position

1

2

3

00 01 DDRAM address (hexadecimal) 40 41

4

5

39

40

02

03 04

..................

26 27

42

43 44

..................

66 67

Figure 4 2-Line Display Display position

1

2

3

4

5

6

7

8

DDRAM address

00 01 02 03 04 05 06 07

For shift left

01 02 03 04 05 06 07 08

40 41 42 43 44 45 46 47

41 42 43 44 45 46 47 48

27 00 01 02 03 04 05 06 For shift right 67 40 41 42 43 44 45 46



HD44780U  Case 2: For a 16-character × 2-line display, the HD44780 can be extended using one 40-output extension driver. See Figure 6. When display shift operation is performed, the DDRAM address shifts. See Figure 6. Display position DDRAM address

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F

HD44780U display

For shift left

Extension driver display

01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50

27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E For shift right 67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E



HD44780U Character Generator ROM (CGROM) The character generator ROM generates 5 × 8 dot or 5 × 10 dot character patterns from 8-bit character codes (Table 4). It can generate 208 5 × 8 dot character patterns and 32 5 × 10 dot character patterns. Userdefined character patterns are also available by mask-programmed ROM. Character Generator RAM (CGRAM) In the character generator RAM, the user can rewrite character patterns by program. For 5 × 8 dots, eight character patterns can be written, and for 5 × 10 dots, four character patterns can be written. Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character patterns stored in CGRAM. See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM. Modifying Character Patterns • Character pattern development procedure The following operations correspond to the numbers listed in Figure 7: 1. Determine the correspondence between character codes and character patterns. 2. Create a listing indicating the correspondence between EPROM addresses and data. 3. Program the character patterns into the EPROM. 4. Send the EPROM to Hitachi. 5. Computer processing on the EPROM is performed at Hitachi to create a character pattern listing, which is sent to the user. 6. If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and samples are sent to the user for evaluation. When it is confirmed by the user that the character patterns are correctly written, mass production of the LSI proceeds at Hitachi.


HD44780U Hitachi

User Start

Computer processing Create character pattern listing

5

Evaluate character patterns No

Determine character patterns

1

Create EPROM address data listing

2

Write EPROM

3

EPROM → Hitachi

4

OK? Yes Art work

M/T

Masking

Trial

Sample

Sample evaluation

OK?

6

No

Yes Mass production Note: For a description of the numbers used in this figure, refer to the preceding page.

Figure 7 Character Pattern Development Procedure


HD44780U • Programming character patterns This section explains the correspondence between addresses and data used to program character patterns in EPROM. The HD44780U character generator ROM can generate 208 5 × 8 dot character patterns and 32 5 × 10 dot character patterns for a total of 240 different character patterns.  Character patterns EPROM address data and character pattern data correspond with each other to form a 5 × 8 or 5 × 10 dot character pattern (Tables 2 and 3). Table 2

Example of Correspondence between EPROM Address Data and Character Pattern (5 × 8 Dots) Data

EPROM Address

LSB A 1 1A 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O 4 O3 O2 O1 O0

0

1

1

0

0

0

Character code Notes: 1. 2. 3. 4. 5. 6.

1

0

0

0

0

0

1

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

1

0

1

0

1

1

0

0

0

1

1

1

1

0

0

1

0

1

0

0

1

0

0

0

1

0

0

0

1

0

1

0

1

1

0

1

1

0

1

1

1

1

0

0

1

1

1

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

0

0

1

0

1

0

0

0

0

0

0

1

0

1

1

0

0

0

0

0

1

1

0

0

0

0

0

0

0

1

1

0

1

0

0

0

0

0

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

0

Cursor position

Line position

EPROM addresses A11 to A4 correspond to a character code. EPROM addresses A3 to A0 specify a line position of the character pattern. EPROM data O4 to O0 correspond to character pattern data. EPROM data O5 to O7 must be specified as 0. A lit display position (black) corresponds to a 1. Line 9 and the following lines must be blanked with 0s for a 5 × 8 dot character fonts.


HD44780U  Handling unused character patterns 1. EPROM data outside the character pattern area: Always input 0s. 2. EPROM data in CGRAM area: Always input 0s. (Input 0s to EPROM addresses 00H to FFH.) 3. EPROM data used when the user does not use any HD44780U character pattern: According to the user application, handled in one of the two ways listed as follows. a. When unused character patterns are not programmed: If an unused character code is written into DDRAM, all its dots are lit. By not programing a character pattern, all of its bits become lit. (This is due to the EPROM being filled with 1s after it is erased.) b. When unused character patterns are programmed as 0s: Nothing is displayed even if unused character codes are written into DDRAM. (This is equivalent to a space.) Table 3

Example of Correspondence between EPROM Address Data and Character Pattern (5 × 10 Dots) EPROM Address

Data

LSB A 1 1A 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O 4 O3 O2 O1 O0

0

1

0

1

0

0

Character code

Notes: 1. 2. 3. 4. 5. 6.

1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

1

0

0

1

1

0

1

0

0

1

1

1

0

0

1

1

0

1

0

0

1

0

0

0

1

0

1

0

1

1

0

0

0

1

0

1

1

0

0

1

1

1

1

0

1

1

1

0

0

0

0

1

1

0

0

0

0

0

0

0

1

1

0

0

1

0

0

0

0

1

1

0

1

0

0

0

0

0

0

1

0

1

1

0

0

0

0

0

1

1

0

0

0

0

0

0

0

1

1

0

1

0

0

0

0

0

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

0

Cursor position

Line position

EPROM addresses A11 to A3 correspond to a character code. EPROM addresses A3 to A0 specify a line position of the character pattern. EPROM data O4 to O0 correspond to character pattern data. EPROM data O5 to O7 must be specified as 0. A lit display position (black) corresponds to a 1. Line 11 and the following lines must be blanked with 0s for a 5 × 10 dot character fonts.


HD44780U Table 4 Lower 4 Bits

Upper 4 Bits

Correspondence between Character Codes and Character Patterns (ROM Code: A00) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010

xxxx0000

CG RAM (1)

xxxx0001

(2)

xxxx0010

(3)

xxxx0011

(4)

xxxx0100

(5)

xxxx0101

(6)

xxxx0110

(7)

xxxx0111

(8)

xxxx1000

(1)

xxxx1001

(2)

xxxx1010

(3)

xxxx1011

(4)

xxxx1100

(5)

xxxx1101

(6)

xxxx1110

(7)

xxxx1111

(8)

1011 1100 1101 1110 1111

Note: The user can specify any pattern for character-generator RAM.


HD44780U Table 4 Lower 4 Bits

Upper 4 Bits

Correspondence between Character Codes and Character Patterns (ROM Code: A02) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

xxxx0000

CG RAM (1)

xxxx0001

(2)

xxxx0010

(3)

xxxx0011

(4)

xxxx0100

(5)

xxxx0101

(6)

xxxx0110

(7)

xxxx0111

(8)

xxxx1000

(1)

xxxx1001

(2)

xxxx1010

(3)

xxxx1011

(4)

xxxx1100

(5)

xxxx1101

(6)

xxxx1110

(7)

xxxx1111

(8)


HD44780U Table 5

Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character Patterns (CGRAM Data)

For 5 × 8 dot character patterns Character Codes (DDRAM data)

CGRAM Address

Character Patterns (CGRAM data)

7 6 5 4 3 2 1 0

5 4 3 2 1 0

7 6 5 4 3 2 1 0

High

High

High

Low

0 0 0 0 * 0 0 0

0 0 0 0 * 0 0 1

0 0 0 0 * 1 1 1

0 0 0

0 0 1

1 1 1

Low 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

1 1 1 1

0 0 1 1

0 1 0 1

* * *

* * * * * *

* * * * * *

Low 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0

1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0

1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0

1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0

0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0

Character pattern (1)

Cursor position

Character pattern (2)

Cursor position

* * *

Notes: 1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types). 2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line regardless of the cursor presence. 3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left). 4. As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bit 3 has no effect, the R display example above can be selected by either character code 00H or 08H. 5. 1 for CGRAM data corresponds to display selection and 0 to non-selection. * Indicates no effect.


HD44780U Table 5

Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character Patterns (CGRAM Data) (cont)

For 5 × 10 dot character patterns Character Codes (DDRAM data)

CGRAM Address

Character Patterns (CGRAM data)

7 6 5 4 3 2 1 0

5 4 3 2 1 0

7 6 5 4 3 2 1 0

High

High

High

Low

0 0 0 0 * 0 0 *

0 0 0 0 * 1 1 *

0 0

1 1

Low 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

1 1 1 1 1 1 1

0 0 0 1 1 1 1

0 1 1 0 0 1 1

1 0 1 0 1 0 1

* * *

* * * * * *

* * * * * *

Low 0 0 1 1 1 1 1 1 1 1 0 *

0 0 0 1 0 0 1 0 0 0 0 *

0 0 1 0 0 0 1 0 0 0 0 *

0 0 1 0 0 0 1 0 0 0 0 *

0 0 0 1 1 1 0 0 0 0 0 *

Character pattern

Cursor position

* * * * *

* * * * * *

* * * * *

* * *

* * * * *

Notes: 1. Character code bits 1 and 2 correspond to CGRAM address bits 4 and 5 (2 bits: 4 types). 2. CGRAM address bits 0 to 3 designate the character pattern line position. The 11th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 11th line data corresponding to the cursor display positon at 0 as the cursor display. If the 11th line data is “1”, “1” bits will light up the 11th line regardless of the cursor presence. Since lines 12 to 16 are not used for display, they can be used for general data RAM. 3. Character pattern row positions are the same as 5 × 8 dot character pattern positions. 4. CGRAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bits 0 and 3 have no effect, the P display example above can be selected by character codes 00H, 01H, 08H, and 09H. 5. 1 for CGRAM data corresponds to display selection and 0 to non-selection. * Indicates no effect.


HD44780U Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas other than the display area. Liquid Crystal Display Driver Circuit The liquid crystal display driver circuit consists of 16 common signal drivers and 40 segment signal drivers. When the character font and number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output non-selection waveforms. Sending serial data always starts at the display data character pattern corresponding to the last address of the display data RAM (DDRAM). Since serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register, the HD44780U drives from the head display. Cursor/Blink Control Circuit The cursor/blink control circuit generates the cursor or character blinking. The cursor or the blinking will appear with the digit located at the display data RAM (DDRAM) address set in the address counter (AC). For example (Figure 8), when the address counter is 08H, the cursor position is displayed at DDRAM address 08H. AC6 AC5 AC4 AC3 AC2 AC1 AC0 AC

0

0

0

1

0

0

0

Display position

1

2

3

4

5

6

7

8

9

10

11

DDRAM address (hexadecimal)

00

01

02

03

04

05

06

07

08

09

0A

1

2

3

4

5

6

7

8

9

10

11

00

01

02

03

04

05

06

07

08

09

0A

40

41

42

43

44

45

46

47

48

49

4A

For a 1-line display

cursor position

For a 2-line display Display position DDRAM address (hexadecimal)

cursor position Note: The cursor or blinking appears when the address counter (AC) selects the character generator RAM (CGRAM). However, the cursor and blinking become meaningless. The cursor or blinking is displayed in the meaningless position when the AC is a CGRAM address.

Figure 8 Cursor/Blink Display Example


HD44780U Interfacing to the MPU The HD44780U can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or 8-bit MPUs. • For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3 are disabled. The data transfer between the HD44780U and the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag and address counter data. • For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.

RS R/W E

DB7

IR7

IR3

BF

AC3

DR7

DR3

DB6

IR6

IR2

AC6

AC2

DR6

DR2

DB5

IR5

IR1

AC5

AC1

DR5

DR1

DB4

IR4

IR0

AC4

AC0

DR4

DR0

Instruction register (IR) write

Busy flag (BF) and address counter (AC) read

Data register (DR) read

Figure 9 4-Bit Transfer Example


HD44780U Reset Function Initializing by Internal Reset Circuit An internal reset circuit automatically initializes the HD44780U when the power is turned on. The following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state until the initialization ends (BF = 1). The busy state lasts for 10 ms after VCC rises to 4.5 V. 1. Display clear 2. Function set: DL = 1; 8-bit interface data N = 0; 1-line display F = 0; 5 × 8 dot character font 3. Display on/off control: D = 0; Display off C = 0; Cursor off B = 0; Blinking off 4. Entry mode set: I/D = 1; Increment by 1 S = 0; No shift Note: If the electrical characteristics conditions listed under the table Power Supply Conditions Using Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the HD44780U. For such a case, initial-ization must be performed by the MPU as explained in the section, Initializing by Instruction.

Instructions Outline Only the instruction register (IR) and the data register (DR) of the HD44780U can be controlled by the MPU. Before starting the internal operation of the HD44780U, control information is temporarily stored into these registers to allow interfacing with various MPUs, which operate at different speeds, or various peripheral control devices. The internal operation of the HD44780U is determined by signals sent from the MPU. These signals, which include register selection signal (RS), read/ write signal (R/W), and the data bus (DB0 to DB7), make up the HD44780U instructions (Table 6). There are four categories of instructions that: • • • •

Designate HD44780U functions, such as display format, data length, etc. Set internal RAM addresses Perform data transfer with internal RAM Perform miscellaneous functions


HD44780U Normally, instructions that perform data transfer with internal RAM are used the most. However, autoincrementation by 1 (or auto-decrementation by 1) of internal HD44780U RAM addresses after each data write can lighten the program load of the MPU. Since the display shift instruction (Table 11) can perform concurrently with display data write, the user can minimize system development time with maximum programming efficiency. When an instruction is being executed for internal operation, no instruction other than the busy flag/address read instruction can be executed. Because the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0 before sending another instruction from the MPU. Note: Be sure the HD44780U is not in the busy state (BF = 0) before sending an instruction from the MPU to the HD44780U. If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. Refer to Table 6 for the list of each instruc-tion execution time. Table 6

Instructions Code

Execution Time (max) (when f cp or f OSC is 270 kHz)

Instruction RS

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description

Clear display

0

0

0

0

0

0

0

0

0

1

Clears entire display and sets DDRAM address 0 in address counter.

Return home

0

0

0

0

0

0

0

0

1

—

Sets DDRAM address 0 in address counter. Also returns display from being shifted to original position. DDRAM contents remain unchanged.

1.52 ms

Entry mode set

0

0

0

0

0

0

0

1

I/D

S

Sets cursor move direction and specifies display shift. These operations are performed during data write and read.

37 µs

Display on/off control

0

0

0

0

0

0

1

D

C

B

Sets entire display (D) on/off, 37 µs cursor on/off (C), and blinking of cursor position character (B).

Cursor or display shift

0

0

0

0

0

1

S/C R/L

—

—

Moves cursor and shifts display without changing DDRAM contents.

Function set

0

0

0

0

1

DL

N

—

—

Sets interface data length 37 µs (DL), number of display lines (N), and character font (F).

Set CGRAM address

0

0

0

1

ACG ACG ACG ACG ACG ACG Sets CGRAM address. CGRAM data is sent and received after this setting.

37 µs

Set DDRAM address

0

0

1

ADD ADD ADD ADD ADD ADD ADD Sets DDRAM address. DDRAM data is sent and received after this setting.

37 µs

Read busy 0 flag & address

1

BF

AC

0 µs

AC

AC

AC

F

AC

AC

AC

Reads busy flag (BF) indicating internal operation is being performed and reads address counter contents.


37 µs

HD44780U Table 6

Instructions (cont) Execution Time (max) (when f cp or f OSC is 270 kHz)

Code Instruction RS

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description

Write data to CG or DDRAM

1

0

Write data

Writes data into DDRAM or CGRAM.

37 µs tADD = 4 µs*

Read data 1 from CG or DDRAM

1

Read data

Reads data from DDRAM or CGRAM.

37 µs tADD = 4 µs*

= 1: = 0: = 1: = 1: = 0: = 1: = 0: = 1: = 1: = 1: = 1: = 0:

Increment Decrement Accompanies display shift Display shift Cursor move Shift to the right Shift to the left 8 bits, DL = 0: 4 bits 2 lines, N = 0: 1 line 5 × 10 dots, F = 0: 5 × 8 dots Internally operating Instructions acceptable

DDRAM: Display data RAM CGRAM: Character generator RAM ACG: CGRAM address ADD: DDRAM address (corresponds to cursor address) AC: Address counter used for both DD and CGRAM addresses

Execution time changes when frequency changes Example: When fcp or fOSC is 250 kHz, 270 37 µs × = 40 µs 250

I/D I/D S S/C S/C R/L R/L DL N F BF BF

Note:

— indicates no effect. * After execution of the CGRAM/DDRAM data write or read instruction, the RAM address counter is incremented or decremented by 1. The RAM address counter is updated after the busy flag turns off. In Figure 10, tADD is the time elapsed after the busy flag turns off until the address counter is updated.

Busy signal (DB7 pin)

Address counter (DB0 to DB6 pins)

Busy state

A

A+1 t ADD

Note: t ADD depends on the operation frequency t ADD = 1.5/(f cp or f OSC ) seconds

Figure 10 Address Counter Update


HD44780U Instruction Description Clear Display Clear display writes space code 20H (character pattern for character code 20H must be a blank pattern) into all DDRAM addresses. It then sets DDRAM address 0 into the address counter, and returns the display to its original status if it was shifted. In other words, the display disappears and the cursor or blinking goes to the left edge of the display (in the first line if 2 lines are displayed). It also sets I/D to 1 (increment mode) in entry mode. S of entry mode does not change. Return Home Return home sets DDRAM address 0 into the address counter, and returns the display to its original status if it was shifted. The DDRAM contents do not change. The cursor or blinking go to the left edge of the display (in the first line if 2 lines are displayed). Entry Mode Set I/D: Increments (I/D = 1) or decrements (I/D = 0) the DDRAM address by 1 when a character code is written into or read from DDRAM. The cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. The same applies to writing and reading of CGRAM. S: Shifts the entire display either to the right (I/D = 0) or to the left (I/D = 1) when S is 1. The display does not shift if S is 0. If S is 1, it will seem as if the cursor does not move but the display does. The display does not shift when reading from DDRAM. Also, writing into or reading out from CGRAM does not shift the display. Display On/Off Control D: The display is on when D is 1 and off when D is 0. When off, the display data remains in DDRAM, but can be displayed instantly by setting D to 1. C: The cursor is displayed when C is 1 and not displayed when C is 0. Even if the cursor disappears, the function of I/D or other specifications will not change during display data write. The cursor is displayed using 5 dots in the 8th line for 5 × 8 dot character font selection and in the 11th line for the 5 × 10 dot character font selection (Figure 13). B: The character indicated by the cursor blinks when B is 1 (Figure 13). The blinking is displayed as switching between all blank dots and displayed characters at a speed of 409.6-ms intervals when fcp or f OSC is 250 kHz. The cursor and blinking can be set to display simultaneously. (The blinking frequency changes according to f OSC or the reciprocal of f cp . For example, when fcp is 270 kHz, 409.6 × 250/270 = 379.2 ms.)


HD44780U Cursor or Display Shift Cursor or display shift shifts the cursor position or display to the right or left without writing or reading display data (Table 7). This function is used to correct or search the display. In a 2-line display, the cursor moves to the second line when it passes the 40th digit of the first line. Note that the first and second line displays will shift at the same time. When the displayed data is shifted repeatedly each line moves only horizontally. The second line display does not shift into the first line position. The address counter (AC) contents will not change if the only action performed is a display shift. Function Set DL: Sets the interface data length. Data is sent or received in 8-bit lengths (DB7 to DB0) when DL is 1, and in 4-bit lengths (DB7 to DB4) when DL is 0.When 4-bit length is selected, data must be sent or received twice. N: Sets the number of display lines. F: Sets the character font. Note: Perform the function at the head of the program before executing any instructions (except for the read busy flag and address instruction). From this point, the function set instruction cannot be executed unless the interface data length is changed. Set CGRAM Address Set CGRAM address sets the CGRAM address binary AAAAAA into the address counter. Data is then written to or read from the MPU for CGRAM.


HD44780U RS Clear display

Code

0

RS Return home

Code

0

RS Entry mode set

Code

0

RS Display on/off control

Code

0

RS Cursor or display shift

Code

0

RS Function set

Code

0

RS Set CGRAM address

Code

0

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0

0

0

0

0

0

0

0

1


0

0

0

0

0

0

1

*

Note: * Don’t care.


0

0

0

0

0

1

I/D

S


0

0

0

0

1

D

C

B


0

0

0

1

S/C

R/L

*

*

Note: * Don’t care.


0

0

1

DL

N

F

*

*


0

1

A

A

A

Higher order bit

A

A

A

Lower order bit

Figure 11 Instruction (1)


HD44780U Set DDRAM Address Set DDRAM address sets the DDRAM address binary AAAAAAA into the address counter. Data is then written to or read from the MPU for DDRAM. However, when N is 0 (1-line display), AAAAAAA can be 00H to 4FH. When N is 1 (2-line display), AAAAAAA can be 00H to 27H for the first line, and 40H to 67H for the second line. Read Busy Flag and Address Read busy flag and address reads the busy flag (BF) indicating that the system is now internally operating on a previously received instruction. If BF is 1, the internal operation is in progress. The next instruction will not be accepted until BF is reset to 0. Check the BF status before the next write operation. At the same time, the value of the address counter in binary AAAAAAA is read out. This address counter is used by both CG and DDRAM addresses, and its value is determined by the previous instruction. The address contents are the same as for instructions set CGRAM address and set DDRAM address. Table 7

Shift Function

S/C

R/L

0

0

Shifts the cursor position to the left. (AC is decremented by one.)

0

1

Shifts the cursor position to the right. (AC is incremented by one.)

1

0

Shifts the entire display to the left. The cursor follows the display shift.

1

1

Shifts the entire display to the right. The cursor follows the display shift.

Table 8

Function Set

N

F

No. of Display Lines

0

0

1

5 × 8 dots

1/8

0

1

1

5 × 10 dots

1/11

1

*

2

5 × 8 dots

1/16

Note:

*

Character Font

Duty Factor

Remarks

Cannot display two lines for 5 × 10 dot character font

Indicates don’t care.


HD44780U

Cursor 5 × 8 dot character font

5 × 10 dot character font

Alternating display

Cursor display example

Blink display example

Figure 12 Cursor and Blinking RS Set DDRAM address

Code

0


1

A

A

A

A

Higher order bit

RS Read busy flag and address

Code

0

A

A

Lower order bit


BF

A

A

A

Higher order bit

A

A

A

Lower order bit



A

A

HD44780U Write Data to CG or DDRAM Write data to CG or DDRAM writes 8-bit binary data DDDDDDDD to CG or DDRAM. To write into CG or DDRAM is determined by the previous specification of the CGRAM or DDRAM address setting. After a write, the address is automatically incremented or decremented by 1 according to the entry mode. The entry mode also determines the display shift. Read Data from CG or DDRAM Read data from CG or DDRAM reads 8-bit binary data DDDDDDDD from CG or DDRAM. The previous designation determines whether CG or DDRAM is to be read. Before entering this read instruction, either CGRAM or DDRAM address set instruction must be executed. If not executed, the first read data will be invalid. When serially executing read instructions, the next address data is normally read from the second read. The address set instructions need not be executed just before this read instruction when shifting the cursor by the cursor shift instruction (when reading out DDRAM). The operation of the cursor shift instruction is the same as the set DDRAM address instruction. After a read, the entry mode automatically increases or decreases the address by 1. However, display shift is not executed regardless of the entry mode. Note: The address counter (AC) is automatically incremented or decremented by 1 after the write instructions to CGRAM or DDRAM are executed. The RAM data selected by the AC cannot be read out at this time even if read instructions are executed. Therefore, to correctly read data, execute either the address set instruction or cursor shift instruction (only with DDRAM), then just before reading the desired data, execute the read instruction from the second time the read instruction is sent. RS Write data to CG or DDRAM

Code

1


D

D

D

D

D

Higher order bits RS Read data from CG or DDRAM

Code

1

D

D

D

Lower order bits


D

D

D

Higher order bits

D

D

D

D

D

Lower order bits



HD44780U Interfacing the HD44780U Interface to MPUs

+ , & % 0)*#

• Interfacing to an 8-bit MPU See Figure 16 for an example of using a I/O port (for a single-chip microcomputer) as an interface device. In this example, P30 to P37 are connected to the data bus DB0 to DB7, and P75 to P77 are connected to E, R/W, and RS, respectively. RS

R/W E

Internal operation

Functioning

Data

Busy

Busy

Instruction write

Busy flag check

Busy flag check

DB7

Not busy

Data

Busy flag check

Instruction write

Figure 15 Example of Busy Flag Check Timing Sequence

H8/325

HD44780U

P30 to P37

P77 P76 P75

8

DB0 to DB7

COM1 to COM16

16

E RS R/W

SEG1 to SEG40

40

LCD

Figure 16 H8/325 Interface (Single-Chip Mode)


HD44780U • Interfacing to a 4-bit MPU The HD44780U can be connected to the I/O port of a 4-bit MPU. If the I/O port has enough bits, 8-bit data can be transferred. Otherwise, one data transfer must be made in two operations for 4-bit data. In this case, the timing sequence becomes somewhat complex. (See Figure 17.) See Figure 18 for an interface example to the HMCS4019R. Note that two cycles are needed for the busy flag check as well as for the data transfer. The 4-bit operation is selected by the program. RS

* $ #

!"()'./

R/W E

Internal operation DB7

Functioning

IR7

IR3

Instruction write

Busy AC3

Not busy AC3

Busy flag check

Busy flag check

D7

D3

Instruction write

Note: IR7 , IR3 are the 7th and 3rd bits of the instruction. AC3 is the 3rd bit of the address counter.

Figure 17 Example of 4-Bit Data Transfer Timing Sequence

HMCS4019R

HD44780

D15

RS

D14

R/W

D13

E

4

R10 to R13

DB4 to DB7

COM1 to COM16

16

LCD

SEG1 to SEG40

40

Figure 18 Example of Interface to HMCS4019R


HD44780U Interface to Liquid Crystal Display Character Font and Number of Lines: The HD44780U can perform two types of displays, 5 × 8 dot and 5 × 10 dot character fonts, each with a cursor. Up to two lines are displayed for 5 × 8 dots and one line for 5 × 10 dots. Therefore, a total of three types of common signals are available (Table 9). The number of lines and font types can be selected by the program. (See Table 6, Instructions.) Connection to HD44780 and Liquid Crystal Display: See Figure 19 for the connection examples. Table 9

Common Signals

Number of Lines

Character Font

Number of Common Signals

Duty Factor

1

5 × 8 dots + cursor

8

1/8

1


11

1/11

2


16

1/16

HD44780 COM1

COM8 SEG1

SEG40 Example of a 5 × 8 dot, 8-character × 1-line display (1/4 bias, 1/8 duty cycle) HD44780 COM1

COM11

SEG1

SEG40 Example of a 5 × 10 dot, 8-character × 1-line display (1/4 bias, 1/11 duty cycle)

Figure 19 Liquid Crystal Display and HD44780 Connections


HD44780U Since five segment signal lines can display one digit, one HD44780U can display up to 8 digits for a 1-line display and 16 digits for a 2-line display. The examples in Figure 19 have unused common signal pins, which always output non-selection waveforms. When the liquid crystal display panel has unused extra scanning lines, connect the extra scanning lines to these common signal pins to avoid any undesirable effects due to crosstalk during the floating state. HD44780 COM1

COM8 COM9

COM16

SEG1

SEG40 Example of a 5 × 8 dot, 8-character × 2-line display (1/5 bias, 1/16 duty cycle)

Figure 19 Liquid Crystal Display and HD44780 Connections (cont)


HD44780U Connection of Changed Matrix Layout: In the preceding examples, the number of lines correspond to the scanning lines. However, the following display examples (Figure 20) are made possible by altering the matrix layout of the liquid crystal display panel. In either case, the only change is the layout. The display characteristics and the number of liquid crystal display characters depend on the number of common signals or on duty factor. Note that the display data RAM (DDRAM) addresses for 4 characters × 2 lines and for 16 characters × 1 line are the same as in Figure 19. HD44780 COM1

COM8 SEG1

SEG40 COM9

COM16 5 × 8 dot, 16-character × 1-line display (1/5 bias, 1/16 duty cycle)

Figure 20 Changed Matrix Layout Displays


HD44780U Power Supply for Liquid Crystal Display Drive Various voltage levels must be applied to pins V1 to V5 of the HD44780U to obtain the liquid crystal display drive waveforms. The voltages must be changed according to the duty factor (Table 10). VLCD is the peak value for the liquid crystal display drive waveforms, and resistance dividing provides voltages V1 to V5 (Figure 21). Table 10

Duty Factor and Power Supply for Liquid Crystal Display Drive Duty Factor 1/8, 1/11

1/16 Bias

Power Supply

1/4

1/5

V1

VCC–1/4 VLCD

VCC–1/5 VLCD

V2

VCC–1/2 VLCD

VCC–2/5 VLCD

V3

VCC–1/2 VLCD

VCC–3/5 VLCD

V4

VCC–3/4 VLCD

VCC–4/5 VLCD

V5

VCC–VLCD

VCC–VLCD

VCC (+5 V)

VCC (+5 V) VCC

VCC R V2

R

V3

R

R VLCD

V4 R V5

R

V1

V1

V2 R R V4 R V5 VR

VR

–5 V

–5 V 1/4 bias (1/8, 1/11 duty cycle)

VLCD

V3

1/5 bias (1/16, duty cycle)

Figure 21 Drive Voltage Supply Example


HD44780U Relationship between Oscillation Frequency and Liquid Crystal Display Frame Frequency The liquid crystal display frame frequencies of Figure 22 apply only when the oscillation frequency is 270 kHz (one clock pulse of 3.7 µs). 1/8 duty cycle COM1

400 clocks 1

2

3

4

8

1

2

11

1

2

1

2

VCC V1 V2 (V3) V4 V5 1 frame 1 frame = 3.7 µs × 400 × 8 = 11850 µs = 11.9 ms 1 Frame frequency = = 84.3 Hz 11.9 ms 1/11 duty cycle COM1

400 clocks 1

2

3

4

VCC V1 V2 (V3) V4 V5 1 frame 1 frame = 3.7 µs × 400 × 11 = 16300 µs = 16.3 ms 1 Frame frequency = = 61.4 Hz 16.3 ms 1/16 duty cycle COM1

200 clocks 1

2

3

4

16

VCC V1 V2 V3 V4 V5 1 frame 1 frame = 3.7 µs × 200 × 16 = 11850 µs = 11.9 ms 1 Frame frequency = = 84.3 Hz 11.9 ms

Figure 22 Frame Frequency


HD44780U Instruction and Display Correspondence • 8-bit operation, 8-digit × 1-line display with internal reset Refer to Table 11 for an example of an 8-digit × 1-line display in 8-bit operation. The HD44780U functions must be set by the function set instruction prior to the display. Since the display data RAM can store data for 80 characters, as explained before, the RAM can be used for displays such as for advertising when combined with the display shift operation. Since the display shift operation changes only the display position with DDRAM contents unchanged, the first display data entered into DDRAM can be output when the return home operation is performed. • 4-bit operation, 8-digit × 1-line display with internal reset The program must set all functions prior to the 4-bit operation (Table 12). When the power is turned on, 8-bit operation is automatically selected and the first write is performed as an 8-bit operation. Since DB0 to DB3 are not connected, a rewrite is then required. However, since one operation is completed in two accesses for 4-bit operation, a rewrite is needed to set the functions (see Table 12). Thus, DB4 to DB7 of the function set instruction is written twice. • 8-bit operation, 8-digit × 2-line display For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be again set after the 8th character is completed. (See Table 13.) Note that the display shift operation is performed for the first and second lines. In the example of Table 13, the display shift is performed when the cursor is on the second line. However, if the shift operation is performed when the cursor is on the first line, both the first and second lines move together. If the shift is repeated, the display of the second line will not move to the first line. The same display will only shift within its own line for the number of times the shift is repeated. Note: When using the internal reset, the electrical characteristics in the Power Supply Conditions Using Internal Reset Circuit table must be satisfied. If not, the HD44780U must be initialized by instructions. See the section, Initializing by Instruction.


HD44780U Table 11 Step No. RS

8-Bit Operation, 8-Digit × 1-Line Display Example with Internal Reset Instruction R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display

Operation

1

Power supply on (the HD44780U is initialized by the internal reset circuit)

Initialized. No display.

2

Function set 0 0 0

Sets to 8-bit operation and selects 1-line display and 5 × 8 dot character font. (Number of display lines and character fonts cannot be changed after step #2.)

3

4

5

6

0

1

1

0

0

*

*

Display on/off control 0 0 0 0

0

0

1

1

1

0

Entry mode set 0 0 0

0

0

0

1

1

0

Write data to CGRAM/DDRAM 1 0 0 1 0 0

1

0

0

0


1

0

0

1

0

7

8 9 10

· · · · · 1

0

0

1


0

0

1

1

1


0

0

0

0

0

Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD/CGRAM. Display is not shifted.

_

Writes H. DDRAM has already been selected by initialization when the power was turned on. The cursor is incremented by one and shifted to the right.

H_

Writes I.

HI_ · · · · ·

Write data to CGRAM/DDRAM 1 0 0 1 0 0 0

Turns on display and cursor. Entire display is in space mode because of initialization.

_

HITACHI_ HITACHI_ ITACHI _

Writes I. Sets mode to shift display at the time of write. Writes a space.


HD44780U Table 11 Step No. RS 11

8-Bit Operation, 8-Digit × 1-Line Display Example with Internal Reset (cont) Instruction R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display


12

13 14 15 16 17 18 19

1

0

1

· · · · · 1

1

1

1

Cursor or display shift 0 0 0 0

0

1

0

0

*

*


0

1

0

0

*

*


0

0

1

1


0

1

1

1

*

*


0

1

0

1

*

*


1

1

0

1

· · · · · Return home 0 0 0

0

0

TACHI M_

Writes M.

· · · · ·


20

21

1

Operation

MICROKO_

Writes O.

MICROKO _

Shifts only the cursor position to the left.

MICROKO _

Shifts only the cursor position to the left.

ICROCO _

Writes C over K. The display moves to the left.

MICROCO _

Shifts the display and cursor position to the right.

MICROCO_

Shifts the display and cursor position to the right.

ICROCOM_

Writes M.

· · · · · 0

0

0

1

0

HITACHI _

Returns both display and cursor to the original position (address 0).



4-Bit Operation, 8-Digit × 1-Line Display Example with Internal Reset Instruction R/W DB7 DB6 DB5 DB4

Display

Operation

1



2

Function set 0 0 0

0

1

0

Sets to 4-bit operation. In this case, operation is handled as 8 bits by initialization, and only this instruction completes with one write.

Function set 0 0 0 0 0 0

0 0

1 *

0 *

Display on/off control 0 0 0 0 0 0 1 1

0 1

0 0

Entry mode set 0 0 0 0 0 0

0 1

0 0

3

4

5

6

Note:

0 1

Write data to CGRAM/DDRAM 1 0 0 1 0 0 1 0 1 0 0 0

Sets 4-bit operation and selects 1-line display and 5 × 8 dot character font. 4-bit operation starts from this step and resetting is necessary. (Number of display lines and character fonts cannot be changed after step #3.) _

_

H_

Turns on display and cursor. Entire display is in space mode because of initialization. Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD/CGRAM. Display is not shifted. Writes H. The cursor is incremented by one and shifts to the right.

The control is the same as for 8-bit operation beyond step #6.



8-Bit Operation, 8-Digit × 2-Line Display Example with Internal Reset Instruction R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display

Operation

1



2

Function set 0 0 0

Sets to 8-bit operation and selects 2-line display and 5 × 8 dot character font.

3

4

5

0

1

1

1

0

*

*

Display on/off control 0 0 0 0

0

0

1

1

1

0


0

0

0

1

1

0


1

0

0

0

0

6

7

8

· · · · ·

Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the DD/CGRAM. Display is not shifted.

_

Writes H. DDRAM has already been selected by initialization when the power was turned on. The cursor is incremented by one and shifted to the right.

H_

· · · · ·


1

0

0

1

Set DDRAM address 0 0 1 1

0

0

0

0

0

Turns on display and cursor. All display is in space mode because of initialization.

_

0

HITACHI_

HITACHI _

Writes I.

Sets DDRAM address so that the cursor is positioned at the head of the second line.


HD44780U Table 13 Step No. RS 9

8-Bit Operation, 8-Digit × 2-Line Display Example with Internal Reset (cont) Instruction R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display


10

11

12

13

1

0

1

· · · · ·

HITACHI M_

1

1

1

1

HITACHI MICROCO_


0

0

1

1

1

HITACHI MICROCO_


1

1

0

1

ITACHI ICROCOM_

0

0

· · · · · Return home 0 0 0

0

0

Writes M.

· · · · ·


14

15

1

Operation

Writes O.

Sets mode to shift display at the time of write. Writes M. Display is shifted to the left. The first and second lines both shift at the same time.

· · · · · 0

0

0

1

0

HITACHI _ MICROCOM

Returns both display and cursor to the original position (address 0).


HD44780U Initializing by Instruction If the power supply conditions for correctly operating the internal reset circuit are not met, initialization by instructions becomes necessary. Refer to Figures 23 and 24 for the procedures on 8-bit and 4-bit initializations, respectively.

Power on

Wait for more than 40 ms after VCC rises to 2.7 V


RS R/WDB7 DB6 DB5 DB4 DB3DB2 DB1 DB0 0 0 0 0 1 1 * * * *

BF cannot be checked before this instruction. Function set (Interface is 8 bits long.)

Wait for more than 4.1 ms

RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 * * * *


Wait for more than 100 µs

RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 * * * *


BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is longer than the execution instuction time. (See Table 6.) RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 N F * * 0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

1

I/D S

Function set (Interface is 8 bits long. Specify the number of display lines and character font.) The number of display lines and character font cannot be changed after this point. Display off Display clear Entry mode set

Initialization ends

Figure 23 8-Bit Interface


HD44780U Power on


RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1



Wait for more than 4.1 ms

RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1


Wait for more than 100 µs

RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 1

BF cannot be checked before this instruction.

RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0

BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is longer than the execution instuction time. (See Table 6.)

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 N 0 1 0 0 0 0

0 F 0 0 0 0 0 1

1 0 * * 0 0 0 0 0 0 0 1 0 0 I/D S

Function set (Interface is 8 bits long.)

Function set (Set interface to be 4 bits long.) Interface is 8 bits in length. Function set (Interface is 4 bits long. Specify the number of display lines and character font.) The number of display lines and character font cannot be changed after this point. Display off Display clear

Initialization ends

Entry mode set

Figure 24 4-Bit Interface


HD44780U Absolute Maximum Ratings* Item

Symbol

Value

Unit

Notes

Power supply voltage (1)

VCC–GND

–0.3 to +7.0

V

1

Power supply voltage (2)

VCC–V5

–0.3 to +13.0

V

1, 2

Input voltage

Vt

–0.3 to VCC +0.3

V

1

Operating temperature

Topr

–30 to +75

°C

Storage temperature

Tstg

–55 to +125

°C

Note:

*

4

If the LSI is used above these absolute maximum ratings, it may become permanently damaged. Using the LSI within the following electrical characteristic limits is strongly recommended for normal operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction and cause poor reliability.


HD44780U DC Characteristics (VCC = 2.7 to 4.5 V, Ta = –30 to +75°C*3) Item

Symbol

Min

Typ

Max

Unit

Input high voltage (1) (except OSC1)

VIH1

0.7V CC

—

VCC

V

6

Input low voltage (1) (except OSC1)

VIL1

–0.3

—

0.55

V

6

Input high voltage (2) (OSC1)

VIH2

0.7V CC

—

VCC

V

15

Input low voltage (2) (OSC1)

VIL2

—

—

0.2V CC

V

15

Output high voltage (1) VOH1 (DB0–DB7)

0.75V CC

—

—

V

–I OH = 0.1 mA

7

Output low voltage (1) (DB0–DB7)

—

—

0.2V CC

V

I OL = 0.1 mA

7

Output high voltage (2) VOH2 (except DB0–DB7)

0.8V CC

—

—

V

–I OH = 0.04 mA

8

Output low voltage (2) (except DB0–DB7)

VOL2

—

—

0.2V CC

V

I OL = 0.04 mA

8

Driver on resistance (COM)

RCOM

—

2

20

kΩ

±Id = 0.05 mA, VLCD = 4 V

13

Driver on resistance (SEG)

RSEG

—

2

30

kΩ

±Id = 0.05 mA, VLCD = 4 V

13

Input leakage current

I LI

–1

—

1

µA

VIN = 0 to VCC

9

Pull-up MOS current (DB0–DB7, RS, R/W)

–I p

10

50

120

µA

VCC = 3 V

Power supply current

I CC

—

150

300

µA

Rf oscillation, external clock VCC = 3 V, f OSC = 270 kHz

LCD voltage

VLCD1

3.0

—

11.0

V

VCC–V5, 1/5 bias 16

VLCD2

3.0

—

11.0

V

VCC–V5, 1/4 bias 16

Note:

*

VOL1

Test Condition Notes*

Refer to the Electrical Characteristics Notes section following these tables.


10, 14

HD44780U AC Characteristics (VCC = 2.7 to 4.5 V, Ta = –30 to +75°C*3) Clock Characteristics Item

Symbol Min

Typ

Max

Unit

External External clock frequency clock External clock duty operation External clock rise time

f cp

125

250

350

kHz

Duty

45

50

55

%

t rcp

—

—

0.2

µs

t fcp

—

—

0.2

µs

190

270

350

kHz

External clock fall time

Rf Clock oscillation frequency f OSC oscillation Note:

*

Test Condition Note* 11

Rf = 75 kΩ, VCC = 3 V

12


Bus Timing Characteristics Write Operation Item

Symbol

Min

Typ

Max

Unit

Test Condition

Enable cycle time

t cycE

1000

—

—

ns

Figure 25

Enable pulse width (high level)

PWEH

450

—

—

Enable rise/fall time

t Er, t Ef

—

—

25

Address set-up time (RS, R/W to E) t AS

60

—

—

Address hold time

t AH

20

—

—

Data set-up time

t DSW

195

—

—

Data hold time

tH

10

—

—

Item

Symbol

Min

Typ

Max

Unit

Test Condition

Enable cycle time

t cycE

1000

—

—

ns

Figure 26


PWEH

450

—

—


t Er, t Ef

—

—

25


60

—

—

Address hold time

t AH

20

—

—

Data delay time

t DDR

—

—

360

Data hold time

t DHR

5

—

—

Read Operation


HD44780U Interface Timing Characteristics with External Driver Item

Symbol

Min

Typ

Max

Unit

Test Condition

High level

t CWH

800

—

—

ns

Figure 27

Low level

t CWL

800

—

—

Clock set-up time

t CSU

500

—

—

Data set-up time

t SU

300

—

—

Data hold time

t DH

300

—

—

M delay time

t DM

–1000

—

1000

Clock rise/fall time

t ct

—

—

200

Clock pulse width

Power Supply Conditions Using Internal Reset Circuit Item

Symbol

Min

Typ

Max

Unit

Test Condition

Power supply rise time

t r CC

0.1

—

10

ms

Figure 28

Power supply off time

t OFF

1

—

—


HD44780U DC Characteristics (VCC = 4.5 to 5.5 V, Ta = –30 to +75°C*3) Item

Symbol

Min

Typ

Max

Unit

Input high voltage (1) (except OSC1)

VIH1

2.2

—

VCC

V

6

Input low voltage (1) (except OSC1)

VIL1

–0.3

—

0.6

V

6

Input high voltage (2) (OSC1)

VIH2

VCC–1.0

—

VCC

V

15

Input low voltage (2) (OSC1)

VIL2

—

—

1.0

V

15

Output high voltage (1) VOH1 (DB0–DB7)

2.4

—

—

V

–I OH = 0.205 mA

7

Output low voltage (1) (DB0–DB7)

—

—

0.4

V

I OL = 1.2 mA

7

Output high voltage (2) VOH2 (except DB0–DB7)

0.9 VCC

—

—

V

–I OH = 0.04 mA

8

Output low voltage (2) (except DB0–DB7)

VOL2

—

—

0.1 VCC

V

I OL = 0.04 mA

8

Driver on resistance (COM)

RCOM

—

2

20

kΩ

±Id = 0.05 mA, VLCD = 4 V

13

Driver on resistance (SEG)

RSEG

—

2

30

kΩ

±Id = 0.05 mA, VLCD = 4 V

13

Input leakage current

I LI

–1

—

1

µA

VIN = 0 to VCC

9

Pull-up MOS current (DB0–DB7, RS, R/W)

–I p

50

125

250

µA

VCC = 5 V

Power supply current

I CC

—

350

600

µA

Rf oscillation, external clock VCC = 5 V, f OSC = 270 kHz

10, 14

LCD voltage

VLCD1

3.0

—

11.0

V

VCC–V5, 1/5 bias

16

VLCD2

3.0

—

11.0

V

VCC–V5, 1/4 bias

16

Note:

*

VOL1

Test Condition

Notes*



HD44780U AC Characteristics (VCC = 4.5 to 5.5 V, Ta = –30 to +75°C*3) Clock Characteristics Item

Symbol Min

Typ

Max

Unit

External External clock frequency clock External clock duty operation External clock rise time

f cp

125

250

350

kHz

11

Duty

45

50

55

%

11

t rcp

—

—

0.2

µs

11

t fcp

—

—

0.2

µs

11

190

270

350

kHz

External clock fall time

Rf Clock oscillation frequency f OSC oscillation Note:

*

Test Condition Notes*

Rf = 91 kΩ VCC = 5.0 V

12


Bus Timing Characteristics Write Operation Item

Symbol

Min

Typ

Max

Unit

Test Condition

Enable cycle time

t cycE

500

—

—

ns

Figure 25


PWEH

230

—

—


t Er, t Ef

—

—

20


40

—

—

Address hold time

t AH

10

—

—

Data set-up time

t DSW

80

—

—

Data hold time

tH

10

—

—

Item

Symbol

Min

Typ

Max

Unit

Test Condition

Enable cycle time

t cycE

500

—

—

ns

Figure 26


PWEH

230

—

—


t Er, t Ef

—

—

20


40

—

—

Address hold time

t AH

10

—

—

Data delay time

t DDR

—

—

160

Data hold time

t DHR

5

—

—

Read Operation


HD44780U Interface Timing Characteristics with External Driver Item

Symbol

Min

Typ

Max

Unit

Test Condition

High level

t CWH

800

—

—

ns

Figure 27

Low level

t CWL

800

—

—

Clock set-up time

t CSU

500

—

—

Data set-up time

t SU

300

—

—

Data hold time

t DH

300

—

—

M delay time

t DM

–1000

—

1000

Clock rise/fall time

t ct

—

—

100

Clock pulse width

Power Supply Conditions Using Internal Reset Circuit Item

Symbol

Min

Typ

Max

Unit

Test Condition

Power supply rise time

t rCC

0.1

—

10

ms

Figure 28

Power supply off time

t OFF

1

—

—


HD44780U Electrical Characteristics Notes 1. All voltage values are referred to GND = 0 V. VCC B V1

A = VCC –V5 B = VCC –V1 A ≥ 1.5 V B ≤ 0.25 × A

A V5

2. 3. 4. 5.

The conditions of V1 and V5 voltages are for proper operation of the LSI and not for the LCD output level. The LCD drive voltage condition for the LCD output level is specified as LCD voltage VLCD.

VCC ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 must be maintained. For die products, specified at 75°C. For die products, specified by the die shipment specification. The following four circuits are I/O pin configurations except for liquid crystal display output. Input pin Pin: E (MOS without pull-up)

Output pin Pins: CL1, CL2, M, D

Pins: RS, R/W (MOS with pull-up) VCC

VCC PMOS

PMOS

VCC PMOS

PMOS

NMOS

NMOS

(pull up MOS) NMOS

I/O Pin Pins: DB0 –DB7 (MOS with pull-up)

VCC

VCC (input circuit)

(pull-up MOS)

PMOS

PMOS Input enable

NMOS VCC NMOS PMOS

Output enable Data

NMOS (output circuit) (tristate)


HD44780U 6. Applies to input pins and I/O pins, excluding the OSC1 pin. 7. Applies to I/O pins. 8. Applies to output pins. 9. Current flowing through pull–up MOSs, excluding output drive MOSs. 10. Input/output current is excluded. When input is at an intermediate level with CMOS, the excessive current flows through the input circuit to the power supply. To avoid this from happening, the input level must be fixed high or low. 11. Applies only to external clock operation. Th Oscillator

Open

Tl

OSC1 0.7 VCC 0.5 VCC 0.3 VCC

OSC2

t rcp Duty =

t fcp

Th × 100% Th + Tl

12. Applies only to the internal oscillator operation using oscillation resistor Rf.

OSC1 Rf OSC2

R f : 75 k Ω ± 2% (when VCC = 3 V) R f : 91 k Ω ± 2% (when VCC = 5 V) Since the oscillation frequency varies depending on the OSC1 and OSC2 pin capacitance, the wiring length to these pins should be minimized.

VCC = 3 V 500

400

400

300 (270)

max. 200

typ.

f OSC (kHz)

f OSC (kHz)

VCC = 5 V 500

300 (270)

max. 200 typ.

min. 100

50

(91)100

R f (k Ω)

150

100

50

(75)

100

min. 150

R f (k Ω)


HD44780U 13. RCOM is the resistance between the power supply pins (VCC, V1, V4, V5) and each common signal pin (COM1 to COM16). RSEG is the resistance between the power supply pins (VCC, V2, V3, V5) and each segment signal pin (SEG1 to SEG40). 14. The following graphs show the relationship between operation frequency and current consumption. VCC = 3 V 1.8

1.6

1.6

1.4

1.4

1.2

1.2

1.0

max.

0.8 typ.

0.6

ICC (mA)

ICC (mA)

VCC = 5 V 1.8

1.0 0.8 0.6

0.4

0.4

0.2

0.2

0.0 0

100

200

300

fOSC or fcp (kHz)

400

500

max. typ.

0.0 0

100

200

300

400

500

fOSC or fcp (kHz)

15. Applies to the OSC1 pin. 16. Each COM and SEG output voltage is within ±0.15 V of the LCD voltage (V CC, V1, V2, V3, V4, V5) when there is no load.


HD44780U Load Circuits Data Bus DB0 to DB7 VCC = 5 V For VCC = 4.5 to 5.5 V

For VCC = 2.7 to 4.5 V 3.9 k Ω

Test point

Test point 90 pF

11 k Ω

IS2074 H diodes

50 pF

External Driver Control Signals: CL1, CL2, D, M Test point 30 pF


HD44780U Timing Characteristics VIH1 VIL1

RS

VIH1 VIL1

tAS

R/W

tAH

VIL1

VIL1 PWEH

tAH tEf

VIH1 VIL1

E

VIH1 VIL1 tEr

tH

tDSW

VIH1 VIL1

DB0 to DB7

VIL1

VIH1 VIL1

Valid data tcycE

Figure 25 Write Operation

VIH1 VIL1

RS

VIH1 VIL1

tAS

tAH

VIH1

R/W

VIH1 PWEH

tAH tEf

VIH1 VIL1

E

VIH1 VIL1

VIL1

tEr tDHR

tDDR

DB0 to DB7

VOH1 VOL1 *

Valid data

VOH1 * VOL1

tcycE

Note:

* VOL1 is assumed to be 0.8 V at 2 MHz operation.

Figure 26 Read Operation


HD44780U tct VOH2

CL1

VOH2

VOL2

tCWH tCSU CL2

tCWH VOH2

VOL2

tCWL tct

tCSU

VOH2 VOL2

D tDH tSU VOH2

M

t DM

Figure 27 Interface Timing with External Driver

VCC

2.7 V/4.5 V*2

0.2 V

0.2 V

0.2 V

tOFF*1

trcc 0.1 ms ≤ trcc ≤ 10 ms

tOFF ≥ 1 ms

Notes: 1. tOFF compensates for the power oscillation period caused by momentary power supply oscillations. 2. Specified at 4.5 V for 5-V operation, and at 2.7 V for 3-V operation. 3. For if 4.5 V is not reached during 5-V operation, the internal reset circuit will not operate normally. In this case, the LSI must be initialized by software. (Refer to the Initializing by Instruction section.)

Figure 28 Internal Power Supply Reset


HD44780U Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.

Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

URL

NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223

Hitachi Europe GmbH Electronic components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322

Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180

Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX

Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.


2981 and 2982 8-Channel Source Drivers Features and Benefits

Description

▪ TTL, DTL, PMOS, or CMOS compatible inputs ▪ 500 mA output source current capability ▪ Transient-protected outputs ▪ Output breakdown voltage to 50 V ▪ DIP or SOIC packaging

Recommended for high-side switching applications that benefit from separate logic and load grounds, these devices encompass load supply voltages to 50 V and output currents to -500 mA. These 8-channel source drivers are useful for interfacing between low-level logic and high-current loads. Typical loads include relays, solenoids, lamps, stepper and/or servo motors, print hammers, and LEDs. All devices may be used with 5 V logic systems — TTL, Schottky TTL, DTL, and 5 V CMOS. The device packages offered are electrically interchangeable, and will withstand a maximum output off voltage of 50 V, and operate to a minimum of 5 V. All devices in this series integrate input current limiting resistors and output transient suppression diodes, and are activated by an active high input.

Packages: Not to scale

18-pin DIP (Package A)

The suffix “A” indicates an 18-lead plastic dual in-line package with copper lead frame for optimum power dissipation. Under normal operating conditions, these devices will sustain 120 mA continuously for each of the eight outputs at an ambient temperature of +50°C and a supply of 15 V. The suffix “LW” package is provided in a 20-pin wide-body SOIC package with improved thermal characteristics compared to the 18-pin SOIC version it replaces (100% pin-compatible electrically). The A2982ELW driver is available for operation over an extended temperature range, down to -40°C.

20-pin SOICW (package LW) (drop-in replacement for discontinued 18-pin SOIC variants)

These packages are lead (Pb) free, with 100% matte-tin leadframe plating.

Simplified Block Diagrams 18-pin DIP (A Package)

20-pin SOICW (LW Package)

(NC pins, 10 and 11, not present on discontinued 18-pin LW package) 29310R


2981 and 2982

8-Channel Source Drivers

Selection Guide Part Number

Package

Packing

Ambient Temperature TA (°C)

A2982ELWTR-T*

20-pin SOICW

1000 per reel

–40 to 85

A2982SLWTR-T

20-pin SOICW

1000 per reel

UDN2981A-T

18-pin DIP

21 per tube

UDN2982A-T

18-pin DIP

21 per tube

–20 to 85

*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is obsolete and notice has been given. Sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new design applications because of obsolescence in the near future. Samples are no longer available. Status date change November 2, 2009. Deadline for receipt of LAST TIME BUY orders is April 30, 2010.

Absolute Maximum Ratings Characteristic

Symbol

Output Voltage Range

Notes

Rating

VCE

Input Voltage

VIN

Output Current

IOUT

Package Power Dissipation

PD

UDN2981 A2982, UDN2982

See graph

Units

5 to 50

V

20

V

20

V

–500

mA

–

–

Range E

–40 to 85

ºC

Range S

Operating Ambient Temperature

TA

–20 to 85

ºC

Maximum Junction Temperature

TJ(max)

150

ºC

Tstg

–55 to 150

ºC

A L L OWA B L E P A C K A G E P OW E R DIS S IP A T ION (W)

Storage Temperature 2.5

2.0

18-P IN DIP , R

JA

= 65 C /W

20-LE AD S OIC , R

JA

= 90 C /W

1.5

1.0

0.5

0 25

50 75 100 A MB IE NT T E MP E R A T UR E C

125

150

Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com


2

2981 and 2982

8-Channel Source Drivers One of Eight Drivers

Typical electrosensitive printer application 18-pin DIP (A Package)

20-pin SOICW (LW Package) R

IN1

1

18

IN 2

2

17

IN3

3

16

IN4

4

15

IN5

5

14

IN6

6

13

IN7

7

12

IN8

8

11

VS

9

10

R R R R R R R

R

L

IN1

1

20

L

IN 2

2

19

L

IN3

3

18

IN4

4

17

IN5

5

16

IN6

6

15

IN7

7

14

IN8

8

13

VS

9

12

NC

10

11

L L L L L

R R R R R R R

L L L L L L L L

NC

Pins 10 and 11 can float; other pins match discontinued 18-pin SOIC: 1 to 9 same, pins 12 to 20 match pins 10 to 18



3

2981 and 2982


ELECTRICAL CHARACTERISTICS1,2 at TA = +25°C (unless otherwise specified). Symbol

Variant

Output Leakage Current3

Characteristic

ICEX

All

Output Sustaining Voltage

VCE(SUS)

All

Collector-Emitter Saturation Voltage

VCE(SAT)

All

2981 Input Current

IIN(ON) 2982

Test Fig.

Min.

Typ.

Max.

Units

VIN = 0.4 V, VS = 50 V

Test Conditions

1

—

—

20

μA

IOUT = -45 mA

—

35

—

—

V

VIN = 2.4 V, IOUT = -100 mA

2

—

1.6

1.8

V

VIN = 2.4 V, IOUT = -225 mA

2

—

1.7

1.9

V

VIN = 2.4 V, IOUT = -350 mA

2

—

1.8

2.0

V

VIN = 2.4 V

3

—

140

200

μA μA

VIN = 3.85 V

3

—

310

450

VIN = 2.4 V

3

—

140

200

μA

VIN = 12 V

3

—

1.25

1.93

mA

2981

VIN = 2.4 V, VCE = 2.0 V

2

-350

—

—

mA

2982

VIN = 2.4 V, VCE = 2.0 V

2

-350

—

—

mA

IS

All

VIN = 2.4 V*, VS = 50 V

4

—

—

10

mA

Clamp Diode Current

IR

All

VR = 50 V, VIN = 0.4 V*

5

—

—

50

μA

Clamp Diode Forward Voltage

VF

All

IF = 350 mA

6

—

1.5

2.0

V

Turn-On Delay

tON

All

0.5 EIN to 0.5 EOUT, RL = 100Ω, VS = 35 V

—

—

0.3

2.0

μs

All

0.5 EIN to 0.5 EOUT, RL = 100Ω, VS = 35 V, See Note

—

—

2.0

10

μs

Output Source Current (Outputs Open) Supply Current Leakage Current

Turn-Off Delay4 1Negative

lOUT

tOFF

current is defined as coming out of (sourcing) the specified device terminal.

2All

unused inputs must be connected to ground. Pull-down resistors (approximately 10 kΩ) are recommended for inputs that are allowed to float while power is being applied to VS.

3All

inputs simultaneously.

4Turn-off delay is influenced by load conditions. Systems applications well below the specified output loading may require timing considerations for some designs, i.e., multiplexed displays or when used in combination with sink drivers in a totem pole configuration.



4

2981 and 2982


TEST FIGURES Figure 1

Figure 2 VS

VS

V

Figure 3 V

V CE

S

I IN

mA

mA

OPEN

I OUT V

VIN

μA

IN

V

IN

I CEX Dwg. No. A-11,083

Dwg. No. A-11,084

Figure 4

Dwg. No. A-11,085

Figure 5

VS

Figure 6

VS

I S mA

OPEN

μA

IR

OPEN

OPEN VF

VIN

VIN

Dwg. No. A-11,086

Dwg. No. A-11,087

V

I

F

Dwg. No. A-11,088



5

2981 and 2982

8-Channel Source Drivers Allowable peak collector current as a function of duty cycle

500

450

450

ALLOWABLE PEAK COLLECTOR CURRENT IN mA AT 70°C

500

400 RECOMMENDED MAXIMUM OUTPUT CURRENT 350

3

300

4 5

250

7

6

8

200 NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 150

100

VS = 15 V

400 RECOMMENDED MAXIMUM OUTPUT CURRENT 350

300

3 4

250

5 6

200

7 8 NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY

150

100

VS = 15 V 50

50

0 0

10

20

30

50 60 40 PER CENT DUTY CYCLE

70

80

0

90

10

0

100

20

30

50 60 40 PER CENT DUTY CYCLE

Dwg. No. A-11,107B

70

80

90

100

Dwg. No. A-11,108B

Input current as a function of input voltage 2.5

2.0 INPUT CURRENT, IIN (mA)

ALLOWABLE PEAK COLLECTOR CURRENT IN mA AT 50°C

UDN2981A and UDN2982A

1.5 UM

IM

X MA

1.0

AL

PIC

TY

0.5

2

4

6

8

10

12

INPUT VOLTAGE (VOLTS) Dwg. No. A-11,115B



6

2981 and 2982

8-Channel Source Drivers A Package, 18-Pin DIP 22.86 ±0.51 18

+0.10 0.25 –0.05 +0.76 6.35 –0.25

+0.38 10.92 –0.25

7.62

A 1

2

5.33 MAX +0.51 3.30 –0.38 2.54 +0.25 1.52 –0.38

0.46 ±0.12

SEATING PLANE

C

All dimensions nominal, not for tooling use (reference JEDEC MS-001 AC) Dimensions in inches Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area

LW Package, 20-Pin SOICW

12.80±0.20 4° ±4

20

20 +0.07 0.27 –0.06

7.50±0.10

10.30±0.33

A

1

2.25

9.50 +0.44 0.84 –0.43

2

1

2

0.65

0.25 20X

SEATING PLANE

0.10 C 0.41 ±0.10

1.27

C

1.27

B PCB Layout Reference View

SEATING PLANE GAUGE PLANE

2.65 MAX 0.20 ±0.10

For Reference Only Dimensions in millimeters (Reference JEDEC MS-013 AC) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown

A Terminal #1 mark area B Reference pad layout (reference IPC SOIC127P1030X265-20M)

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances



7

2981 and 2982


Copyright ©1977-2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com



8
















SCLS041G − DECEMBER 1982 − REVISED FEBRUARY 2004

D 8-Bit Serial-In, Parallel-Out Shift D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State Outputs Can Drive Up D D D D D

SN54HC595 . . . J OR W PACKAGE SN74HC595 . . . D, DB, DW, N, OR NS PACKAGE (TOP VIEW)

QB QC QD QE QF QG QH GND

To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 13 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Shift Register Has Direct Clear

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

9

VCC QA SER OE RCLK SRCLK SRCLR QH′

description/ordering information The ’HC595 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.

QC QB NC VCC QA

SN54HC595 . . . FK PACKAGE (TOP VIEW)

5

17

6

16

7

15

8

14 9 10 11 12 13

SER OE NC RCLK SRCLK

SRCLR

3 2 1 20 19 18

QH

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

4

GND NC Q H′

QD QE NC QF QG

NC − No internal connection

ORDERING INFORMATION PACKAGE†

TA PDIP − N

TOP-SIDE MARKING

Tube of 25

SN74HC595N

Tube of 40

SN74HC595D

Reel of 2500

SN74HC595DR

Reel of 250

SN74HC595DT

Tube of 40

SN74HC595DW

Reel of 2000

SN74HC595DWR

SOP − NS

Reel of 2000

SN74HC595NSR

HC595

SSOP − DB

Reel of 2000

SN74HC595DBR

HC595

CDIP − J

Tube of 25

SNJ54HC595J

SNJ54HC595J

CFP − W

Tube of 150

SNJ54HC595W

SNJ54HC595W

LCCC − FK

Tube of 55

SNJ54HC595FK

SOIC − D −40°C to 85°C SOIC − DW

−55°C −55 C to 125 125°C C

ORDERABLE PART NUMBER

SN74HC595N

HC595

HC595

SNJ54HC595FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+

Copyright  2004, Texas Instruments Incorporated

'*%$"# $')!" " 1 2 !)) '!!&"&# !& "&#"&* %)&## ",&.#& "&*+ !)) ",& '*%$"# '*%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+

Papan informasi..., Evy Christian Sri Nugroho, FT UI, 2010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1


FUNCTION TABLE INPUTS

2

FUNCTION

SER

SRCLK

SRCLR

RCLK

OE

X

X

X

X

H

Outputs QA−QH are disabled.

X

X

X

X

L

Outputs QA−QH are enabled.

X

X

L

X

X

Shift register is cleared.

L

↑

H

X

X

First stage of the shift register goes low. Other stages store the data of previous stage, respectively.

H

↑

H

X

X

First stage of the shift register goes high. Other stages store the data of previous stage, respectively.

X

X

X

↑

X

Shift-register data is stored in the storage register.



logic diagram (positive logic) OE RCLK SRCLR SRCLK SER

13 12 10 11 14

1D C1 R

3R C3 3S

15

2S 2R C2 R

3R C3 3S

1

2S 2R C2 R

3R C3 3S

2

2S 2R C2 R

3R C3 3S

3

2S 2R C2 R

3R C3 3S

4

2S 2R C2 R

3R C3 3S

5

2S 2R C2 R

3R C3 3S

6

2S 2R C2 R

3R C3 3S

7

9

QA

QB

QC

QD

QE

QF

QG

QH QH′

Pin numbers shown are for the D, DB, DW, J, N, NS, and W packages.


3


timing diagram SRCLK

SER

RCLK

SRCLR

OE

ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ

QA

QB

QC

QD

QE

QF

QG

QH

QH’ NOTE:

4

ÎÎÎÎ ÎÎÎÎ

implies that the output is in 3-State mode.



absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3) SN54HC595 VCC VIH

Supply voltage

High-level input voltage

VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V

VIL VI VO ∆t/∆v‡

Low-level input voltage

MIN

NOM

MAX

2

5

6

Input transition rise/fall time

VCC = 6 V

MAX

2

5

6

3.15

3.15

4.2

4.2

0 VCC = 2 V VCC = 4.5 V

NOM

1.5

0

Output voltage

MIN

1.5

VCC = 4.5 V VCC = 6 V

Input voltage

SN74HC595

0.5

1.35

1.35

1.8

1.8 0 0

V

V

0.5

VCC VCC

UNIT

VCC VCC

1000

1000

500

500

400

400

V V V

ns

TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.


5


electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER

VOH

SN74HC595

MIN

2V

1.9

1.998

1.9

1.9

IOH = −20 µA

4.5 V

4.4

4.499

4.4

4.4

6V

5.9

5.999

5.9

5.9

3.98

4.3

3.7

3.84

3.98

4.3

3.7

3.84

5.48

5.8

5.2

5.34

VI = VIH or VIL

QH′, IOH = −4 mA QH′, IOH = −5.2 mA QA−QH, IOH = −7.8 mA IOL = 20 µA

VI = VIH or VIL

QH′, IOL = 4 mA QA−QH, IOL = 6 mA QH′, IOL = 5.2 mA QA−QH, IOL = 7.8 mA

4.5 V 6V

5.48

5.8

MIN

MAX

5.2

MIN

MAX

V

5.34

2V

0.002

0.1

0.1

0.1

4.5 V

0.001

0.1

0.1

0.1

6V

0.001

0.1

0.1

0.1

0.17

0.26

0.4

0.33

0.17

0.26

0.4

0.33

0.15

0.26

0.4

0.33

0.15

0.26

0.4

0.33

4.5 V 6V

UNIT

V

II IOZ

VI = VCC or 0 VO = VCC or 0,

6V

±0.1

±100

±1000

±1000

nA

QA−QH

6V

±0.01

±0.5

±10

±5

µA

ICC

VI = VCC or 0,

IO = 0

6V

8

160

80

µA

10

10

10

pF

Ci

6

SN54HC595

VCC

QA−QH, IOH = −6 mA

VOL

TA = 25°C TYP MAX

TEST CONDITIONS

2V to 6 V

3



timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC

fclock

Clock frequency

SRCLK or RCLK high or low tw

Pulse duration SRCLR low

SER before SRCLK↑

SRCLK↑ before RCLK↑† tsu

Setup time SRCLR low before RCLK↑

SRCLR high (inactive) before SRCLK↑

th

Hold time, SER after SRCLK SRCLK↑

TA = 25°C MIN MAX

SN54HC595 MIN

MAX

SN74HC595 MIN

MAX

2V

6

4.2

5

4.5 V

31

21

25

6V

36

25

29

2V

80

120

100

4.5 V

16

24

20

6V

14

20

17

2V

80

120

100

4.5 V

16

24

20

6V

14

20

17

2V

100

150

125

4.5 V

20

30

25

6V

17

25

21

2V

75

113

94

4.5 V

15

23

19

6V

13

19

16

2V

50

75

65

4.5 V

10

15

13

6V

9

13

11

2V

50

75

60

4.5 V

10

15

12

6V

9

13

11

2V

0

0

0

4.5 V

0

0

0

6V

0

0

0

UNIT

MHz

ns

ns

ns

† This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.


7


switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER

FROM (INPUT)

TO (OUTPUT)

fmax

SRCLK

QH H′

tpd RCLK

tPHL

ten

tdis

QA−QH

SRCLR

QH H′

OE

QA−QH

OE

QA−QH

QA−QH tt QH H′

VCC

MIN

TA = 25°C TYP MAX

SN54HC595 MIN

MAX

SN74HC595 MIN

2V

6

26

4.2

5

4.5 V

31

38

21

25

6V

36

42

25

29

MAX

UNIT

MHz

2V

50

160

240

200

4.5 V

17

32

48

40

6V

14

27

41

34

2V

50

150

225

187

4.5 V

17

30

45

37

6V

14

26

38

32

2V

51

175

261

219

4.5 V

18

35

52

44

6V

15

30

44

37

2V

40

150

225

187

4.5 V

15

30

45

37

6V

13

26

38

32

2V

42

200

300

250

4.5 V

23

40

60

50

6V

20

34

51

43

2V

28

60

90

75

4.5 V

8

12

18

15

6V

6

10

15

13

2V

28

75

110

95

4.5 V

8

15

22

19

6V

6

13

19

16

ns

ns

ns

ns

ns

switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER

tpd

ten

FROM (INPUT)

TO (OUTPUT)

RCLK

QA−QH

OE

QA−QH

tt

QA−QH

VCC

MIN

TA = 25°C TYP MAX

SN54HC595 MIN

MAX

SN74HC595 MIN

MAX

2V

60

200

300

250

4.5 V

22

40

60

50

6V

19

34

51

43

2V

70

200

298

250

4.5 V

23

40

60

50

6V

19

34

51

43

2V

45

210

315

265

4.5 V

17

42

63

53

6V

13

36

53

45

UNIT

ns

ns

ns

operating characteristics, TA = 25°C PARAMETER Cpd

8

Power dissipation capacitance

TEST CONDITIONS

TYP

UNIT

No load

400

pF



PARAMETER MEASUREMENT INFORMATION VCC S1

Test Point

From Output Under Test

PARAMETER

RL

CL (see Note A)

tPZH

ten

1 kΩ

tPZL tPHZ

tdis

S2

RL

tPLZ

Data Input

VCC

50% 10%

50%

VCC 0V

In-Phase Output

50% 10%

tPHL 90%

90%

tr tPHL Out-ofPhase Output

90%

tf

Closed

Closed

Open

Open

Open

VCC

th

90%

90%

VCC 50% 10% 0 V tf

50% 10%

Output Control (Low-Level Enabling)

VCC 50%

50% 0V

tPZL VOH 50% 10% V OL tf

Output Waveform 1 (See Note B)

tPLZ ≈VCC 50%

90%

VOH VOL

Output Waveform 2 (See Note B)

≈VCC 10%

tPZH

tPLH 50% 10%

Open

VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES

50%

tPLH

Open

tr

VOLTAGE WAVEFORMS PULSE DURATIONS

50%

Closed

0V

0V

Input

Closed

tsu

0V

50%

Open

50%

50% tw

Low-Level Pulse

50 pF or 150 pF

Reference Input

VCC 50%

S2

50 pF or 150 pF

LOAD CIRCUIT

High-Level Pulse

S1

50 pF

1 kΩ

−−

tpd or tt

CL

VOL

tPHZ 50%

90%

VOH ≈0 V

tr

VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS

NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time, with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms


9


MECHANICAL DATA MCFP004A– JANUARY 1995 – REVISED FEBRUARY 2002

W (R-GDFP-F16)

CERAMIC DUAL FLATPACK Base and Seating Plane

0.285 (7,24) 0.245 (6,22)

0.045 (1,14) 0.026 (0,66)

0.006 (0,15) 0.080 (2,03) 0.055 (1,40)

0.004 (0,10)

0.305 (7,75) MAX 1

0.019 (0,48) 0.015 (0,38)

16

0.050 (1,27)

0.430 (10,92) 0.370 (9,40)

0.005 (0,13) MIN 4 Places

8

9

0.360 (9,14) 0.250 (6,35)

0.360 (9,14) 0.250 (6,35) 4040180-3 / C 02/02

NOTES: A. B. C. D. E.

All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP-1F16 and JEDEC MO-092AC


MECHANICAL DATA MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

18

17

16

15

14

13

NO. OF TERMINALS **

12

19

11

20

10

B

A MIN

MAX

MIN

MAX

20

0.342 (8,69)

0.358 (9,09)

0.307 (7,80)

0.358 (9,09)

28

0.442 (11,23)

0.458 (11,63)

0.406 (10,31)

0.458 (11,63)

21

9

22

8

44

0.640 (16,26)

0.660 (16,76)

0.495 (12,58)

0.560 (14,22)

23

7

52

0.739 (18,78)

0.761 (19,32)

0.495 (12,58)

0.560 (14,22)

24

6 68

0.938 (23,83)

0.962 (24,43)

0.850 (21,6)

0.858 (21,8)

84

1.141 (28,99)

1.165 (29,59)

1.047 (26,6)

1.063 (27,0)

B SQ A SQ

25

5

26

27

28

1

2

3

4 0.080 (2,03) 0.064 (1,63)

0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25)

0.055 (1,40) 0.045 (1,14)

0.045 (1,14) 0.035 (0,89)

0.045 (1,14) 0.035 (0,89)

0.028 (0,71) 0.022 (0,54) 0.050 (1,27)

4040140 / D 10/96 NOTES: A. B. C. D. E.

All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004



MECHANICAL DATA MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001

D (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

8 PINS SHOWN 0.020 (0,51) 0.014 (0,35)

0.050 (1,27) 8

0.010 (0,25)

5

0.008 (0,20) NOM

0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)

Gage Plane 1

4

0.010 (0,25) 0°– 8°

A

0.044 (1,12) 0.016 (0,40)

Seating Plane 0.010 (0,25) 0.004 (0,10)

0.069 (1,75) MAX

PINS **

0.004 (0,10)

8

14

16

A MAX

0.197 (5,00)

0.344 (8,75)

0.394 (10,00)

A MIN

0.189 (4,80)

0.337 (8,55)

0.386 (9,80)

DIM

4040047/E 09/01 NOTES: A. B. C. D.

All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012


MECHANICAL DATA MSOI003E – JANUARY 1995 – REVISED SEPTEMBER 2001

DW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

16 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 9

0.050 (1,27) 16

0.010 (0,25)

0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM

0.299 (7,59) 0.291 (7,39)

Gage Plane 0.010 (0,25) 1

8

0°– 8°

0.050 (1,27) 0.016 (0,40)

A

Seating Plane 0.104 (2,65) MAX

0.012 (0,30) 0.004 (0,10) PINS **

0.004 (0,10)

16

18

20

24

28

A MAX

0.410 (10,41)

0.462 (11,73)

0.510 (12,95)

0.610 (15,49)

0.710 (18,03)

A MIN

0.400 (10,16)

0.453 (11,51)

0.500 (12,70)

0.600 (15,24)

0.700 (17,78)

DIM

4040000/E 08/01 NOTES: A. B. C. D.

All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013



MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN 0,38 0,22

0,65 28

0,15 M

15

0,25 0,09 8,20 7,40

5,60 5,00

Gage Plane 1

14

0,25

A

0°–ā8°

0,95 0,55

Seating Plane 2,00 MAX

0,10

0,05 MIN

PINS **

14

16

20

24

28

30

38

A MAX

6,50

6,50

7,50

8,50

10,50

10,50

12,90

A MIN

5,90

5,90

6,90

7,90

9,90

9,90

12,30

DIM

4040065 /E 12/01 NOTES: A. B. C. D.

All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150


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