Trend era Digital Sistem yang semakin kompleks Digital & Analog IC (Mixed Signal) Hardware & Software design SoC, SoPC
Menghasilkan … Desain yang komplek Waktu desain yang cepat untuk memenuhi kebutuhan pasar 2
Sistem Terinegrasi
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SoP System-on-Package (SoP) / System-inPackage (SiP)
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Mengapa perlu HW+SW Hardware Cepat Mahal
Software Fleksibel Lebih lambat
Hardware + Software ?
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Kamera Digital
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Macem-macem metode penyusunan rangkaian digital IC digital diskret Programmable logic: SPLD CPLD FPGA
ASIC
IC digital Diskret IC kegunaan umum, banyak terdapat di pasaran satu IC hanya mewakili satu fungsi, contoh: IC NAND 7400 IC BCD counter 7490 dll
Logika Digital Digital Logic Function Product AND (&) Sum OR (|)
3 Inputs
Black Box
Truth Table
SUM of PRODUCTS Boolean Logic Minimisation
Connect Standard Logic Chips Very Simple Glue Logic FIXED Logic
Transistor Switches
Kebutuhan suatu rangkaian digital yang programmable Penyusunan rangkaian digital kompleks menggunakan IC digital diskret butuh banyak IC IC digital diskret kurang fleksibel harus merangkai hardware engineer digital ingin membuat suatu rangkaian digital yang bisa dimodif via software
Rangkaian Digital Programmable Suatu Piranti (IC) berisi gerbang-gerbang digital dan flip flop, yang interkoneksi antar gerbangnya bisa diprogram via software Macam-macamnya: SPLD CPLD FPGA
SPLD Simple programmable logic device Ukuran kecil Hanya terdiri dari dua jenis gate (AND dan OR), jumlahnya tergantung seri IC nya Ada 2 jenis: PLA (Programmable Logic Array) PAL (Programmable Array Logic)
(PAL & PLA, nampak sama tetapi sedikit beda)
PLA (programmable logic array)
Programmable planes
*Hanya bisa diprogram sekali
PAL (programmable array logic)
Programmable plane
*Bisa diprogram berkali-kali
PLD - Sum of Products Array input gerbang AND diikuti gerbang OR A
B
C
Programmable switch or fuse
f1 = A • B • C + A • B • C
f2 = A • B + A • B • C
AND plane
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PLD - Macrocell Array input gerbang AND diikuti gerbang OR dan flipflop Select A
B
Enable
C
f1 Flip-flop MUX D
Q
Clock
AND plane 16
CPLD Complex programmable logic device Extend the density of SPLD CPLD seperti SPLD tetapi mempunyai banyak gate, ditambah dengan flip flop Terdiri dari lapisan interconnect, gates , dan flip flop Bisa diprogram berkali-kali, electrically erasable & programmable
Complex PLDs CPLDs Programmable PLD Blocks Programmable Interconnects Electrically Erasable links CPLD Architecture
Feedback Outputs
CPLD
CPLD Structure Integration of several PLD blocks with a programmable interconnect on a single chip PLD Block
• • •
• • •
I/O Block
PLD Block
I/O Block
I/O Block
• • •
Interconnection Matrix
I/O Block
• • •
PLD Block
PLD Block
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CPLD Families
CPLD Example – Altera MAX7000
EPM7000 Series Block Diagram
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CPLD Example –Altera MAX7000
EPM7000 Series Device Macrocell
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Pemrograman PLD Memprogram SPLD dan CPLD berarti memprogram interkoneksi/plane Pada perpotongan jalur input dengan jalur gate terdapat suatu fuse yang menghubungkan input dengan jalur gate Membuat suatu koneksi berarti membiarkan fuse terhubung, sedangkan memutus suatu koneksi berarti menghilangkan fuse
ASIC Application specific integrated circuit IC yang hanya digunakan untuk keperluan tertentu Biasanya designer IC langsung memesan ASIC ke pabrik IC Kompleksitas rangkaian dalam IC cukup tinggi, jadi tidak muat pada CPLD Dibuat dalam jumlah yang terbatas Sangat mahal
Full-Custom ASIC layout-based the designer draws each polygon “by hand” More compact design but longer design time only for analogue and high(est) volumes 26
Cell-Based ASIC used predefined building blocks (“cells”) designer creates a schematic that interconnects these cells layout = placement & interconnection of cells for “functionality” or “time-to market” driven design 27
FPGA Field programmable gate array Kapasitas sangat besar Menggunakan blok RAM FPGA untuk konfigurasi interkoneksi Karena memakai RAM, maka interkoneksi hilang jika powernya mati Fungsi FPGA adalah untuk prototype sebelum dijadikan ASIC
What is an FPGA? An FPGA (Field Programmable Gate Array) is a reprogrammable chip which contains hundreds of thousands of logic gates that internally connects together to build complex digital circuitry.
1/5/2017
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Benefits FPGA’s Real-time analysisof of high-rate data streams
(Performance) Deterministic hardware dedicated to every task (Reliability) Nonrecurring engineering expenses (Reconfigurability ) Radiation Hardened and Program Integrity. (Durability) Flexible and rapid prototyping (Development)
Field Programmable Gate Arrays (FPGAs)
FPGA Types
(Anti-fuse technology)
FPGA Families
SRAM-type FPGA Interconnect Architecture
Diamond switch
Horizontal routing (interconnect) channel PSM: Programmable Switch Matrix (for making connections between interconnects of different channels). The structure shown only allows i-to-i connections Vertical routing channels
CLB: Configuration Logic Block (programmable logic cell)
SRAM-type FPGA Interconnect Architecture (contd)
Cell Connection Matrix (CCM)
PSM
Arsitektur FPGA
Gate Array Each chip is prefabricated with an array of identical gates or cells. The chip is “customized” by fabricating routing layers on top. Time to market, cost 37
Field programmable gate array Chips are prefabricated with logic blocks and interconnects. Logic and interconnects can be programmed (erased and reprogrammed) by users. No fabrication is needed. Cost efficient for medium complexity (< 1M gates) designs 38
FPGA - Generic Structure Logic block
FPGA building blocks:
I/O
I/O
I/O
Programmable logic blocks Implement combinatorial and sequential logic Programmable interconnect Wires to connect inputs and outputs to logic blocks Programmable I/O blocks Special logic blocks at the periphery of device for external connections
Interconnection switches
I/O 39
Other FPGA Building Blocks Clock distribution Embedded memory blocks Special purpose blocks: DSP blocks: Hardware multipliers, adders and registers
Embedded microprocessors/microcontrollers High-speed serial transceivers
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FPGA – Basic Logic Element LUT to implement combinatorial logic Register for sequential circuits Additional logic (not shown):
Carry logic for arithmetic functions Expansion logic for functions requiring more than 4 inputs Select
Out A B C D
LUT
D
Q
Clock 41
Look-Up Tables (LUT) Look-up table with N-inputs can be used to implement any combinatorial function of N inputs LUT is programmed with the truth-table A B C D
LUT
Z
LUT implementation A B Z C D
Truth-table
Gate implementation
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LUT Implementation X1 X2
Example: 3-input LUT Configuration memory cells Based on multiplexers (pass transistors) LUT entries stored in configuration memory cells
X3
0/1 0/1 0/1 0/1 0/1
F
0/1 0/1 0/1 43
Programmable Interconnect Interconnect hierarchy (not shown) Fast local interconnect Horizontal and vertical lines of various lengths LE
LE
Switch Matrix
LE
LE
Switch Matrix
LE
LE 44
Switch Matrix Operation Before Programming
After Programming
6 pass transistors per switch matrix interconnect point Pass transistors act as programmable switches Pass transistor gates are driven by configuration memory cells 45
Special Features Clock management PLL,DLL Eliminate clock skew between external clock input and on-chip clock Low-skew global clock distribution network
Support for various interface standards High-speed serial I/Os Embedded processor cores DSP blocks 46
Configuration Storage Elements Static Random Access Memory (SRAM) each switch is a pass transistor controlled by the state of an SRAM bit FPGA needs to be configured at power-on
Flash Erasable Programmable ROM (Flash) each switch is a floating-gate transistor that can be turned off by injecting charge onto its gate. FPGA itself holds the program reprogrammable, even in-circuit
Fusible Links (“Antifuse”) Forms a forms a low resistance path when electrically programmed one-time programmable in special programming machine radiation tolerant 47
FPGA Vendors & Device Families Xilinx Virtex-II/Virtex-4: Featurepacked high-performance SRAM-based FPGA Spartan 3: low-cost feature reduced version CoolRunner: CPLDs
Altera Stratix/Stratix-II High-performance SRAM-based FPGAs
Cyclone/Cyclone-II Low-cost feature reduced version for cost-critical applications
MAX3000/7000 CPLDs MAX-II: Flash-based FPGA
Actel Anti-fuse based FPGAs Radiation tolerant
Flash-based FPGAs
Lattice Flash-based FPGAs CPLDs (EEPROM)
QuickLogic ViaLink-based FPGAs 48
State of the Art in FPGAs Xilinx’s top of the line FPGA 65nm process technology 550MHz RAM blocks 6-input LUTs
Serial connectivity Ethernet MACs Rocket I/O serial 6.5 GBps PCI Express endpoint
Enhanced DSP blocks (25x18-bit MAC) 1760 pin BGA with 1200 I/O EasyPath 49
FPGA Design Flow
Xilinx Design Flow 50
Macam FPGA berdasar pemrogramannya
