IKI20210 Pengantar Organisasi Komputer Kuliah no. 6b: Memori
Bobby Nazief (
[email protected]) Johny Moningka (
[email protected])
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Agenda ° Review teknologi memori ° Static RAM (SRAM) ° Dynamic RAM (DRAM) ° Struktur Memori Besar
° Referensi: Ch. 5 (Computer Organization, Harmarcher)
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Review: 5 Komponen Komputer
Computer Processor
Memory
(active)
(passive)
Control (“brain”)
Datapath (“brawn”)
Devices
Keyboard, Mouse
Input (where programs, data live when running)
Disk (permanent storages)
Output
D i s p l a y, Printer
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Istilah/Jenis Semikonduktor Memori RAM
--R a n d o m A c c e s s M e m o r y
time taken to access any arbitrary location in memory is constant
SRAM
--S t a t i c R A M
A RAM chip design technology (see later)
DRAM
-- D y n a m i c R A M
A RAM chip design technology (see later)
ROM
--R e a d O n l y M e m o r y
R O M s a r e R A M s w i t h d a t a b u i l t -i n w h e n t h e chip is created. Usually stores BIOS info. Older uses included storage of bootstrap info
PROM
--P r o g r a m m a b l e R O M
E P R O M --E r a s a b l e P R O M
A ROM which can be programmed A PROM which can be programmed, erased by exposure to UV radiation
E E R O M – Electrical E P R O M
A PROM programmed & erased electrically
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Istilah …?? Tambahan istilah:
SIMM
Single In- Line Memory Module
DIMM
Dual In- Line Memory Module
FPM RAM
Fast Page- M o d e R A M
EDO RAM
Extended-d a t a -o u t R A M
A p a c k a g i n g t e c h n o l o g y ( s i n g l e 3 2 -bit data path) A p a c k a g i n g t e c h n o l o g y ( d u a l 3 2 -bit data paths) An older technology capable of about 60ns cycle time More modern FPM RAM, exploiting address coherency (see cachelater) capable of about 20ns access speed SDRAM
Synchronous DRAM Synchronous Dynamic RAM; allows access speeds as low as about 10ns PC 100, PC133, PC2100, PC2600 => memory product you can buy
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Connection: Memory - Processor
Processor
k-bit address bus
MAR
Memory Sampai 2k addressable locations
n-bit data bus Panjang word = n bits
MDR
Control lines, R/W, MFC, etc.
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Konsep Dasar ° Memory: akses per byte • Transfer dilakukan per-word (cepat, kelipatan bytes) • Misalkan: 32-bit komputer => address 32 bit Kemampuan addressing: 2 ^ 32 = 4 Gbytes • Jika transfer data per-word: 32 bit (data bus) => 4 bytes • Bytes mana yang diakses dari kemungkinan word tsb? - Perlu 2 bits untuk menentukan bytes yang mana dari word - Sisa bit: 30 bits digunakan untuk address word 7
Organisasi Internal Memori ° Bentuk array: terdiri dari sel memori • Sel berisi 1 bit informasi • Baris dari sel membentuk untaian satu word • Contoh: 16 x 8 memori - memori SRAM mengandung 16 words - setiap words terdiri dari 8 bit data - Kapasitas memori: 16 x 8 = 128 bits • Decoder digunakan untuk memilih baris word mana yang akan diakses - Tipikal SRAM, array 1 dimensi => indeks dari baris pada array tersebut.
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Review: Static RAM Cell 6-Transistor SRAM Cell 0
Latch => menyimpan state 1 bit Transistor T bertindak sebagai switch Contoh: state 1
T
T 0
b’
°
word (row select)
1
1
b
Latch dapat berubah dengan: - put bit value pada b dan b’ - word line pull high (select)
Write: 1. Drive bit lines sesuai dengan bit (mis. b = 1, b’ = 0) 2. Select row => store nilai b dan b’ menjadi state latch
°
Read: 1. Precharge (set) bit lines high 2. Select row 3. Sense amp mendeteksi bit lines mana yang low => state bit
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Static RAM (SRAM) ° SRAM dapat menyimpan “state” (isi RAM) selama terdapat “tegangan” power supply ° Sangat cepat, 10 nano-detik ° Densitas rendah (bits per chip) => memerlukan 6 transistor per-sel => mahal ° Pilihan teknologi memori: sangat cepat dengan kapasitas kecil
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Contoh: 1-level-decode SRAM (16 x 8) Word => 8 bit data b7
b7’
b1
b1’
b0
b0’
W0
W1
A0 A1
Address Address decoder decoder
A2
memory cells
A3 W15
16 words
Input/output lines
sense/write sense/write amps amps
sense/write sense/write amps amps
sense/write sense/write amps amps
d7
d1
d0
R/W’
CS
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Review: 1-Transistor Memory Cell (DRAM) Kapasitor menyimpan state 1 (charged) atau 0 (discharge) Perlu refresh!
row select
° Write:
T
• 1. Drive bit line • 2. Select row (T sebagai switch)
° Read:
C bit
• 1. Select row • 2. Sense Amp (terhubung dengan bit line): sense & drives sesuai dengan value (threshold) • 3. Write: restore the value (high or low)
° Refresh • Just do a dummy read to every cell.
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Dynamic RAM (DRAM) ° Slower than SRAM • access time ~60 ns (paling cepat: 35 ns)
° Nonpersistant • every row must be accessed every ~1 ms (refreshed)
° Densitas tinggi: 1 transistor/bit • Lebih murah dari SRAM • ~$1/MByte [2002]
° Fragile • electrical noise, light, radiation
° Pilihan teknologi memori untuk kapasitas besar dan “low cost” 13
Classical DRAM Organization (square) bit (data) lines r o w d e c o d e r
row address
Each intersection represents a 1-T DRAM Cell
RAM Cell Array
word (row) select
Column Selector & I/O Circuits
data
Column Address
° Row and Column Address together: • Select 1 bit a time
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Contoh: 1 K x 1 memory chip 5-bit decoder
W0 W1 W31
32 x 32 Memory cell array
5-bit row address Sense/write circuitry
32 x 1 Output/input multiplexer
R/W CS
5-bit column address 10-bit address Data Input/Output (1 bit)
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Struktur Memori Besar (1/4) Misalkan: Chip memori 128 x 8
8 data lines
17 address lines /CS
Chips select
/WE /CS
/WE
Function
Data Lines
H
X
not selected
Hi - Z
L
H
Read
data at location on address lines
L
L
Write
write data on data lines to address on address lines
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Contoh: Struktur 1 MB (2/4) 1 MB dapat dikonstruksi dengan organisasi 8 chips memori 128 KB (8 x 128 x 8 = 1 MB) The address space is
This will be chip 0
partitioned into 128K blocks;
This will be chip 1
b l o c k 0 h a s a d d r e s s e s 0 -- 1 2 8 K -1 b l o c k 1 h a s a d d r e s s e s 1 2 8 K -- 2 5 6 K-1 b l o c k 2 h a s a d d r e s s e s 2 5 6 K -- 3 8 4 K -1 : : : : b l o c k 7 h a s a d d r e s s e s 8 9 6 K -- 1 0 2 4 K -1
This will be chip 7
Berapa banyak bits yang diperlukan untuk alamat pada chips? memilih chips yang mana? 17
Contoh: Pembagian field address (3/4) 1MB requires 20 bits of address, Ide: membagi field address menjadi 2 yakni: bits untuk memilih chips dan address pada field tsb. B i t s 1 9 -- 1 7 ( 3 a d d r e s s b i t s )
B i t s 1 6 -- 0 ( 1 7 a d d r e s s b i t s )
17 bits select the address in each 128KB block (== each chip)
3 address bits select on of the 8 128KB blocks (chips)
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Contoh: Struktur 1MB memory (4/4) 20 Address Lines 1 7 A d d r e s s L i n e s A 1 6 -- A 0
Write 3 Address Lines A 1 9 --A 1 7
3- to- 8 /WE
decoder
Data Lines
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Ringkasan (.. To remember) ° DRAM lambat tapi murah dan kapasitas besar (densitas tinggi) • Pilihan untuk memberikan kapasitas BESAR pada sistem memori.
° SRAM cepat tapi mahal dan kapasitas kecil • Pilihan untuk menyediakan sistem memori yang waktu aksesnya CEPAT.
° Struktur memori besar dapat dibangun dari kumpulan chips memori kecil: • Field alamat dibagi: field address dan field untuk memilih chips/memori yang mana. • Next topic: Trend teknologi memori (go to: http//www.tomshardware.com, search SDRAM guide)
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