Jobsheet Praktikum REGISTER

1

Jobsheet Praktikum REGISTER

A. Tujuan Kegiatan Praktikum 1-4 : Setelah mempraktekkan Topik ini, anda diharapkan dapat : 1. Mengetahui fungsi dan prinsip kerja register. 2. Menerapkan register SISO, PISO, SIPO dan PIPO dalam rangkaian elektronika digital. 3. Mengetahui operasi dan aplikasi ring shift counter dan Johnson shift counter. 4. Mengetahui konsep three-state (logika 3-keadaan) pada komponen elektronika digital. B. Dasar Teori Kegiatan Praktikum 1-4 Register merupakan komponen elektronika digital yang berfungsi untuk menyimpan secara sementara sekumpulan bit. Bit data yang dioperasikan dalam sistem digital kadang-kadang perlu disimpan, dipindahkan, atau digeser ke kiri atau ke kanan satu posisi atau lebih. Register geser dapat menangani perpindahan bit data paralel dan serial, serta dapat digunakan untuk mengonversi dari paralel ke serial dan serial ke paralel. Ada 4 macam register geser, yaitu: 1. Serial-In, Serial-Out (SISO) 2. Serial-In, Parallel-Out (SIPO) 3. Parallel-In, Serial-Out (PISO) 4. Parallel-In Parallel-Out (PIPO) IC 74LS164 merupakan register geser 8-bit serial-in, parallel out. IC ini mempunyai 2 masukan seri yaitu A dan B yang secara sinkron dibaca oleh clock yang dipicu pada tepi positif (CLK). Selain itu ada kaki Master-Reset ( MR ) yang me-reset kedelapan flip-flop ketika diberi logika LOW. Setiap pulsa clock tepi positif akan menggeser bit data 1 posisi ke kanan sehingga bit data pertama yang dimasukkan akan dikeluarkan pada Q7 setelah delapan pulsa clock. Kaki 7 dihubungkan ke GND dan kaki 14 dihubungkan ke +5V. Susunan kaki IC 74LS164 dapat dilihat dalam Gambar 4.1.

Lab Teknik Digital

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Jobsheet Praktikum 1 2 3 4 5 6 7

A B Q0 Q1 Q2 Q3 GND

VCC Q7 Q6 Q5 Q4 MR CLK

14 13 12 11 10 9 8

74LS164

Gambar 1.1 Susunan Kaki IC 74LS164

IC 74LS165 merupakan register geser 8-bit serial/parallel-in, serial-out. IC ini mempunyai kaki masukan seri SER dan 8 masukan paralel yaitu P0 – P7 serta 2 luaran serial Q7 dan komplemennya Q7 yang merupakan luaran flip-flop paling kanan. Untuk memasukkan 8 bit masukan secara paralel, kaki PL harus berlogika LOW. Selain itu terdapat 2 masukan clock, yaitu CLK1 yang dipicu pada tepi positif untuk menggeser bit data 1 posisi ke kanan dan CLK2 yang merupakan clock enable aktif-LOW untuk memulai/menghentikan operasi geser dengan meng-enable atau men-disable clock. Kaki 8 dihubungkan ke GND dan kaki 16 dihubungkan ke +5V. Susunan kaki IC 74LS165 dapat dilihat dalam Gambar 4.2. 1 2 3 4 5 6 7 8

PL CLK1 P4 P5 P6 P7 Q7 GND

VCC CLK2 P3 P2 P1 P0 SER Q7

16 15 14 13 12 11 10 9

74LS165


IC 74LS373 merupakan latch oktal yang terdiri dari 8 D-flip-flop dan 8 buffer (penyangga) tri-state yang digunakan untuk menahan data 8-bit. Komponen ini mempunyai 8 masukan, yaitu D0 – D7 dan 8 luaran, yaitu Q0 –Q7. Selain itu ada juga masukan LE (latch enable - aktif-HIGH) yang dihubungkan dengan masukan clock flip-flop dan masukan OE (output enable - aktif-LOW) untuk mengijinkan buffer tri-state agar mengeluarkan data pada luaran. Kaki 10 dihubungkan ke GND dan kaki 20 dihubungkan ke +5V. Susunan kaki IC 74LS373 dapat dilihat dalam Gambar 4.3.

Lab Teknik Digital

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Jobsheet Praktikum 1 2 3 4 5 6 7 8 9 10

OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND

VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 LE

20 19 18 17 16 15 14 13 12 11

PIN74373


D. Lembar Praktikum 1. Alat dan Bahan IC 74164

1 buah

IC 74165

1 buah

IC 7414

1 buah

IC 74373

1 buah

Resistor 10K Ω

9 buah

Resistor 220 Ω

8 buah

Resistor 100 Ω

1 buah

Kapasitor 0,47 µF

1 buah

LED

8 buah

Project Board

1 buah

Power Supply DC

1 buah

Pinset

1 buah

Dipswitch

1 buah

Push Button

1 buah

Multimeter

1 buah

Jumper

secukupnya

Lab Teknik Digital

Jobsheet Praktikum

4

2. Kesehatan dan Keselamatan kerja (a) Periksalah kelengkapan alat dan bahan sebelum digunakan. (b) Pelajari dan pahami petunjuk praktikum pada lembar kegiatan praktikum. (c) Pastikan tegangan keluaran catu daya sesuai yang dibutuhkan. (d) Sebelum catu daya dihidupkan hubungi dosen pendamping untuk mengecek kebenaran rangkaian. (e) Yakinkan tempat anda aman dari sengatan listrik. (f) Hati-hati dalam penggunaan peralatan praktikum !

Lab Teknik Digital

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Jobsheet Praktikum

3. Langkah percobaan 1 1. Rakitlah rangkaian seperti Gambar 1.4 pada project board. Hubungkan kaki SER pada luaran rangkaian DIPSWITCH. 2. Ukur catu daya DC sebesar +5V. Matikan catu daya dan hubungkan ke rangkaian. 3. Hidupkan catu daya. Cek luaran rangkaian DIPSWITCH, catat sisi saklar ke sebelah mana yang mengeluarkan tegangan +5V (logika 1) serta tegangan 0V (logika 0). Matikan catu daya.

Catatan: - LED nyala berarti logika 1 dan LED mati berarti logika 0. - Kondisi luaran rangkaian push button: 1 jika dilepas, 0 jika ditekan,  saat ditekan, saat dilepas Input

+5V

10k SW-PB 1

A 74LS14

B 74LS14 2

3

4

100 0,47uF

0 1

10 11 12 13 14 3 4 5 6 2 15 1

SER P0 P1 P2 P3 P4 P5 P6 P7

Output

Q7 Q7

9 7 220

CLK1 CLK2 PL 74LS165

Gambar 1.4 Rangkaian untuk Percobaan Register Geser SISO

4. Beri logika 0 pada kaki CLK2 dan logika 1 pada kaki PL dan hidupkan catu daya. 5. Beri logika 1 pada kaki SER, tekan push button, dan catat kondisi LED pada kaki Q7 dan Q7 pada baris pertama Tabel 4.1. 6. Ulangi langkah 5 sesuai dengan logika lain seperti yang tertera dalam Tabel 4.1 untuk baris 2 dan seterusnya.

Lab Teknik Digital

LED

6

Jobsheet Praktikum Tabel 1.1 Data Hasil Percobaan Register Geser SISO MASUKAN SER CLK1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1

Lab Teknik Digital

                   

LUARAN Q7 Q7

7

Jobsheet Praktikum

4. Langkah Percobaan 2 1. Rakitlah rangkaian seperti Gambar 1.5 pada project board. Hubungkan kaki P0 – P7 pada luaran rangkaian DIPSWITCH. 0

Input

+5V

10k SW-PB 1

A 74LS14

B 74LS14 2

3

100 0,47uF

4

10 11 12 13 14 3 4 5 6 2 15 1

SER P0 P1 P2 P3 P4 P5 P6 P7

Output

Q7 Q7

9 7 220

CLK1 CLK2 PL

LED

74LS165

Gambar 1.5 Rangkaian untuk Percobaan Register Geser PISO

2. Ukur catu daya DC sebesar +5V. Matikan catu daya dan hubungkan ke rangkaian. 3. Hidupkan catu daya. Cek luaran rangkaian DIPSWITCH, catat sisi saklar ke sebelah mana yang mengeluarkan tegangan +5V (logika 1) serta tegangan 0V (logika 0). Matikan catu daya.

Catatan: - LED nyala berarti logika 1 dan LED mati berarti logika 0. - Kondisi luaran rangkaian push button: 1 jika dilepas, 0 jika ditekan,  saat ditekan,  saat dilepas 4. Beri logika 0 pada kaki SER dan hidupkan catu daya. 5. Beri logika 0 pada kaki P0 – P7, logika 1 pada kaki PL dan CLK2. Tekan push button, dan catat kondisi LED pada kaki Q7 dan Q7 pada baris pertama Tabel 4.2. 6. Beri logika 10101011 pada kaki P0P1P2P3P4P5P6P7, logika 1 pada kaki CLK2 dan logika 0 pada kaki PL . Catat kondisi LED pada kaki Q7 dan Q7 pada baris kedua Tabel 4.2.

Lab Teknik Digital

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Jobsheet Praktikum

7. Ulangi langkah 5 sesuai dengan kombinasi logika lain seperti yang tertera dalam Tabel 4.2 untuk baris 3 dan seterusnya. DATA HASIL PERCOBAAN

Tabel 1.2 Data Hasil Percobaan Register Geser PISO MASUKAN P0 P1 P2

P3

P4

P5

P6

P7

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Lab Teknik Digital

PL 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CLK2

CLK1

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0

 X               

LUARAN Q7 Q7

9

Jobsheet Praktikum

5. Langkah Percobaan 3 1. Rakitlah rangkaian seperti Gambar 1.6 pada project board. Hubungkan kaki A, B dan MR pada luaran rangkaian DIPSWITCH.

+5V

Output Input

10k SW-PB 1

A 74LS14

1 2

A B

B 74LS14 2

3

100

4

8 9

0,47uF

CLK MR

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

74LS164

3 4 5 6 10 11 12 13 220

Gambar 1.6 Rangkaian untuk Percobaan Register Geser SIPO

2. Ukur catu daya DC sebesar +5V. Matikan catu daya dan hubungkan ke rangkaian. 3. Hidupkan catu daya. Cek luaran rangkaian DIPSWITCH, catat sisi saklar ke sebelah mana yang mengeluarkan tegangan +5V (logika 1) serta tegangan 0V (logika 0). Matikan catu daya.

Catatan: - LED nyala berarti logika 1 dan LED mati berarti logika 0. - Kondisi luaran rangkaian push button: 1 jika dilepas, 0 jika ditekan,  saat ditekan,  saat dilepas 4. Beri logika 1 dan 0 pada kaki A dan B, logika 1 pada kaki MR . Biarkan push button dalam kondisi tidak ditekan, dan catat kondisi LED pada kaki Q0 – Q7 pada baris pertama Tabel 4.3. 5. Ulangi langkah 4 sesuai dengan kombinasi logika lain seperti yang tertera dalam Tabel 4.3 untuk baris 2 dan seterusnya.

Lab Teknik Digital

LED

10

Jobsheet Praktikum DATA HASIL PERCOBAAN

Tabel 1.3 Data Hasil Percobaan Register Geser SIPO MASUKAN A B 1 0 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

LUARAN MR 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1

Lab Teknik Digital

CLK 1 1 1             X   

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

11

Jobsheet Praktikum 6. Langkah Percobaan 4 1. Rakitlah rangkaian seperti Gambar 1.7 pada project board. INPUT

9

16 15 14 13 12 11 10

+5V

RESPACK3 10k ohm

1 2 3 4 5 6 7 8

OUTPUT

220 ohm 1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

3 4 7 8 13 14 17 18 1 11

SW-DIP8

D0 D1 D2 D3 D4 D5 D6 D7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

OE LE 74LS373

Gambar 1.7 Rangkaian untuk Percobaan Register Geser PIPO

2. Ukur catu daya DC sebesar +5V. Matikan catu daya dan hubungkan catu daya ke rangkaian.

Catatan:

-

Logika

1

diperoleh

dengan

menghubungkan pada +5V sedangkan logika 0 diperoleh dengan menghubungkan pada GND. - LED nyala berarti logika 1 dan LED mati berarti logika 0. 3. Cek kondisi saklar, catat arah switch untuk menunjukkan logika 0 dan 1. 4. Hidupkan catu daya. 5. Beri logika 0 pada kaki OE . 6. Beri logika 1 pada kaki LE, beri logika 01100000 pada masukan D0– D7 dan catat logika luaran Q0-Y7 dalam Tabel 4.4 baris 1. 7. Beri logika 0 pada kaki LE, beri logika 10011111 pada masukan D0– D7 dan catat logika luaran Q0–Q7 dalam Tabel 4.4 baris 2.

Lab Teknik Digital

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Jobsheet Praktikum

8. Ulangi langkah 6 dan 7 untuk kombinasi logika lain seperti yang tertera dalam Tabel 4.4 untuk baris 3 - 10. 9. Beri logika 1 pada kaki OE 10. Beri logika sembarang (0 atau 1) pada masukan D0–D7 dan kaki LE, serta catat luaran Q0–Q7 (dengan LED) pada baris 11 Tabel 4.4. 11. Cek luaran Q0–Q7 dengan logic probe dan catat hasilnya dalam baris terakhir Tabel 4.4.

DATA HASIL PERCOBAAN Tabel 1.4 Data Hasil Percobaan Register Geser PIPO OE 0 0 0 0 0 0 0 0 0 0 1 1

LE 1 0 1 0 1 0 1 0 1 0

D0 0 1 1 0 1 0 1 1 1 0

MASUKAN D1 D2 D3 1 1 0 0 0 1 0 1 0 1 0 1 1 1 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0

D4 0 1 0 1 0 0 1 1 1 0

D5 0 1 0 0 0 0 1 0 1 0

D6 0 1 0 1 0 0 1 0 1 0

D7 0 1 0 0 0 1 1 0 1 0

Q0

Q1

Q2

LUARAN Q3 Q4 Q5

TUGAS

1. Tuliskan tabel fungsi IC 74LS164, 74LS165, dan 74LS373 beserta penjelasan tentang prinsip kerjanya. 2. Jelaskan tentang ring-shift counter dan Johnson-shift counter beserta operasi kerjanya. 3. Sebutkan jenis-jenis latch berdasarkan pemicuannya dan jelaskan perbedaan diantara jenis-jenis tersebut. Berikan contoh untuk masingmasing latch tersebut. 4. Desain pengonversi serial ke paralel 16-bit.

Lab Teknik Digital

Q6

Q7

Jobsheet Praktikum

13

Analisa _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________

Lab Teknik Digital

Jobsheet Praktikum

14

Kesimpulan _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________

Lab Teknik Digital

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Jobsheet Praktikum ADC-DAC

A. Tujuan Kegiatan Praktikum 5-6 : Setelah mempraktekkan Topik ini, anda diharapkan dapat : 1. Mengetahui prinsip kerja ADC dan DAC. 2. Mengetahui toleransi kesalahan ADC dan ketelitian DAC. 3. Memahami spesifikasi ADC dan DAC yang diberikan oleh data book. 4. Mengaplikasikan ADC dan DAC dalam rangkaian elektronika digital. B. Dasar Teori Kegiatan Praktikum 5-6 Analog-to-Digital Converter (ADC) merupakan peranti yang mengubah besaran kontinyu (suhu, tekanan, intensitas cahaya, dan lain-lain) menjadi besaran diskrit (digital). ADC0808 adalah peranti CMOS monolitik dengan konverter analog-ke-digital 8-bit, multiplekser 8-kanal dan logika kontrol yang kompatibel dengan mikroprosesor. ADC ini mempunyai toleransi kesalahan  ½ LSB serta dapat mengonversi dalam waktu 100 s dengan luaran yang ditahan oleh buffer tri-state.

1 2 3 4 5 6 7 8 9 10 11 12 13 14

IN-3 IN-4 IN-5 IN-6 IN-7 START EOC 2-5 ENABLE CLOCK VCC ref(+) GND 2-7

IN-2 IN-1 IN-0 ADD-A ADD-B ADD-C ALE msb2-1 2-2 2-3 2-4 lsb2-8 ref(-) 2-6

28 27 26 25 24 23 22 21 20 19 18 17 16 15

ADC0808

Gambar 1.1 Susunan Kaki ADC0808 IC ADC0808 mempunyai 8 masukan analog (IN-0 – IN-7) yang dapat dipilih melalui alamat 3-bit (ADD-A – ADD-C). ADC akan memulai konversi dengan kecepatan sesuai dengan frekuensi CLOCK yang diberikan setelah sinyal START diaktifkan. Setelah konversi selesai, maka sinyal EOC (End of Conversion) akan aktif untuk menandai bahwa data pada kaki luaran (2-1/MSB – 28

/LSB) dapat dibaca dengan bantuan sinyal OE (Output Enable). Komponen ini

Lab Teknik Digital

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Jobsheet Praktikum

mempunyai 2 kaki untuk tegangan referensi yaitu ref(+) dan ref(-). Sedangkan kaki 13 dihubungkan ke GND dan kaki 11 dihubungkan ke VCC. Susunan kaki IC ADC0808 dapat dilihat dalam Gambar 5.1. Digital-to-Analog Converter (DAC) adalah sebuah peranti yang mengonversi dari besaran diskrit (digital) ke besaran kontinyu. DAC0808 merupakan IC DAC monolitik 8-bit dengan ketelitian relatif 0,19% sampai 0,78%. IC ini mempunyai masukan digital 8-bit (A1/MSB – A8/LSB) dan satu luaran yaitu Iout. Sebagai acuan, diperlukan tegangan referensi Vrf(+) dan Vrf(-). Selain itu ada pula kaki COMP untuk menghubungkan kapasitor kompensasi dengan VEE. Catu daya yang diperlukan untuk IC ini ada 3 macam, yaitu kaki 13 untuk VCC, kaki 3 untuk VEE dan kaki 2 untuk GND. Susunan kaki IC DAC0808 dapat dilihat dalam Gambar 5.2. 1 2 3 4 5 6 7 8

NC GND Vee Iout msbA1 A2 A3 A4

COMP Vrf(-) Vrf(+) Vcc lsbA8 A7 A6 A5

16 15 14 13 12 11 10 9

DAC0808

Gambar 1.2 Susunan Kaki IC DAC0808

D. Lembar Praktikum 1. Alat dan Bahan IC ADC0808

1 buah

IC DAC0808

1 buah

LM 741

1 buah

Resistor 10K Ω

8 buah

Resistor 5K Ω

3 buah

Resistor 220 Ω

9 buah

Resistor 100 Ω

2 buah

Variabel Resistor

1 buah

Kapasitor 0,1 µF

1 buah

LED

9 buah

Function Generator

1 buah

Lab Teknik Digital

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Jobsheet Praktikum Multimeter Digital

1 buah

Power Supply DC ±15VDC (simetris)

1 buah

Power Supply DC (non simetris)

1 buah

Project Board

1 buah

Push Button

2 buah

Dipswitch

1 buah

Pinset

1 buah

Jumper

secukupnya


Lab Teknik Digital

4

Jobsheet Praktikum 3. Langkah percobaan 5 1. Rakitlah rangkaian seperti Gambar 1.3 pada project board.

Vref(+) OUTPUT

INPUT P1

26 27 28 1 2 3 4 5 25 24 23 13 16

IN-0 IN-1 IN-2 IN-3 IN-4 IN-5 IN-6 IN-7 ADD-A ADD-B ADD-C

msb2-1 2-2 2-3 2-4 2-5 2-6 2-7 lsb2-8 EOC

CLOCK GND ref(-)

21 20 19 18 8 15 14 17 7

10

CLOCK VCC

ENABLE

9

VCC Vref(+)

VCC 11 12

VCC ref(+)

START ALE

6 22

100

ADC0808 100

Gambar 1.3 Rangkaian untuk Percobaan ADC0808

2. Ukur catu daya DC sebesar +5,12V. Matikan catu daya dan hubungkan ke rangkaian pada VCC dan Vref(+). Catatan: - LED nyala berarti logika 1 dan LED mati berarti logika 0. 3. Set frekuensi function generator pada 10kHz. Matikan function generator dan hubungkan ke rangkaian pada kaki CLOCK. 4. Hubungkan multimeter pada luaran resistor variabel untuk mengukur Vinput. 5. Hidupkan catu daya dan function generator. 6. Set resistor variabel untuk memperoleh Vinput sebesar 0V, tekan push button pada kaki START/ALE, lalu lepaskan. 7. Tekan push button pada kaki OE, baca logika pada LED output. Catat hasilnya dalam Tabel 5.1. Lepaskan push button. 8. Ulangi langkah 6 dan 7 dengan Vinput yang lain seperti yang tertera dalam Tabel 5.1.

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Jobsheet Praktikum DATA HASIL PERCOBAAN Tabel 1.1 Data Hasil Percobaan IC ADC0808 fCLOCK Vref(+) Vinput (Hz) (V) (V)

2-1

2-2

OUTPUT (Praktek) Biner -3 2 2-4 2-5 2-6 2-7

2-8

2-1

2-2

OUTPUT (Hitung) Biner -3 2 2-4 2-5 2-6

0 0,4 0,8 1,2 1,6 2,0 2,4 2,8 3,2 3,6 4,0 4,4 4,8 5,0 5,1

ANALISIS DATA HASIL PERCOBAAN 1. Gambarkan kurva transfer Analog-ke-Digital (kode output A/D (biner) fungsi Vinput) dalam Gambar 1. 2. Hitung kode output (hitung) dalam biner untuk setiap Vinput dan masukkan dalam Tabel 5.1. Rumus: N 

Vinput  Vref () x 256 Vref ( )  Vref ()

dimana N = kode output dalam desimal. 3. Gambarkan garis linier untuk kode output (hitung) fungsi Vinput dalam Gambar 1. 4. Hitung toleransi kesalahan untuk masing-masing data dan buatkan tabel toleransi kesalahannya. 5. Hitung toleransi kesalahan keseluruhan untuk ADC0808.

Lab Teknik Digital

2-7

2-8

6

Jobsheet Praktikum 4. Langkah Percobaan 6 1. Rakitlah rangkaian seperti Gambar 1.4 pada project board.

INPUT

9

16 15 14 13 12 11 10

VCC

VCC

1 2 3 4 5 6 7 8

13

RESPACK3 10k ohm

5k

Vref(+) VCC 5k

4

5k

2 6 3 LM741

COMP

16

5

SW-DIP8

Iout

14 15 2

7

msbA1 A2 A3 A4 A5 A6 A7 lsbA8

Vrf(+) Vrf(-) GND

4 1

5 6 7 8 9 10 11 12

Vcc

16 15 14 13 12 11 10 9

Vee

1 2 3 4 5 6 7 8

C1 0,1uF

3

DAC0808

P2 VEE VEE

Gambar 1.4 Rangkaian untuk Percobaan DAC0808

2. Ukur catu daya DC sebesar +5,12V. Matikan catu daya dan hubungkan ke rangkaian pada kaki VCC DAC0808, Vref(+) DAC0808 dan kedelapan kaki resistor 10k. 3. Ukur catu daya simetris DC pada +6V dan –6V. Matikan catu daya dan hubungkan ke rangkaian pada kaki VCC LM741 dan kaki VEE LM741 dan DAC0808. 4. Hubungkan multimeter pada luaran LM741 untuk mengukur Vout. 5. Hidupkan catu daya. 6. Beri logika 0 pada kaki A1 – A8. 7. Ukur Vout dan catat hasilnya dalam Tabel 5.2. 8. Ulangi langkah 6 dan 7 dengan kombinasi logika lain seperti yang tertera dalam Tabel 5.2.

Lab Teknik Digital

OUT

7

Jobsheet Praktikum DATA HASIL PERCOBAAN Tabel 1.2 Data Hasil Percobaan IC DAC0808 Vref(+) (V)

A1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

A2 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1

A3 0 0 1 1 0 1 1 0 1 1 0 0 1 1 1

INPUT (Biner) A4 A5 0 0 1 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 1 0 0 1 1 1 1 0 1 1 1 1

A6 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1

A7 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

A8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Vout Praktek (V)

Vout Hitung (V)

ANALISIS DATA HASIL PERCOBAAN 1. Gambarkan kurva transfer Digital-ke-Analog (Vout fungsi kode input biner) dalam Gambar 2. 2. Hitung Vout hitung dalam Volt untuk setiap kode input biner dan masukkan dalam Tabel 5.2. Rumus:  A1 A2 A3 A4 A5 A6 A7 A8  Vout  Vref () x         4 8 16 32 64 128 256   2

3. Gambarkan garis linier untuk Vout hitung fungsi kode input biner dalam Gambar 2. 4. Hitung kesalahan relatif (dalam Volt dan %) untuk masing-masing data dan buatkan tabel kesalahan relatifnya. 5. Hitung kesalahan relatif keseluruhan (dalam Volt dan %) untuk DAC0808.

Lab Teknik Digital

Jobsheet Praktikum

8

TUGAS 1. Rancang rangkaian pengubah analog ke digital dengan IC ADC0804 dan berikan penjelasannya 2. Apakah fungsi op-amp dalam rangkaian DAC? 3. Jika Iref (arus referensi) diganti menjadi 1,5 mA, apa pengaruhnya terhadap Iout dan Vout?

Lab Teknik Digital

Jobsheet Praktikum

9

Analisa _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________

Lab Teknik Digital

Jobsheet Praktikum

10

Kesimpulan _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________

Lab Teknik Digital

1

Jobsheet Praktikum MEMORI

A. Tujuan Kegiatan Praktikum 7 : Setelah mempraktekkan Topik ini, anda diharapkan dapat : 1. Mengetahui prinsip kerja penulisan dan pembacaan data dalam memori. 2. Mengetahui dan memahami pengalamatan memori dan pendekodean memori sebagai komponen elektronika digital. B. Dasar Teori Kegiatan Praktikum 7 Dalam sistem digital, memori digunakan untuk menyimpan data/informasi secara sementara atau permanen. Secara umum memori terbagi menjadi dua, yaitu RAM: Random Access Memory dan ROM: Read Only Memory. RAM dapat ditulisi dan dibaca secara acak, sedangkan ROM hanya dapat dibaca setelah ditulis datanya. IC memori 6116 merupakan salah satu RAM statik berkapasitas 16.384 bit atau 2 kbyte. IC 6116 mempunyai 8 jalur data (D0-D7) dan 11 jalur alamat (A0-A10). Untuk menulis data digunakan sinyal W (aktif LOW) dan untuk membaca data digunakan sinyal G (aktif LOW). Kaki E (aktif LOW) digunakan untuk mengijinkan memori menulis atau membaca data pada jalur data. Kaki 12 dihubungkan ke GND dan kaki 24 dihubungkan ke +5V. Susunan kaki IC memori 6116 dapat dilihat dalam Gambar 6.1. 8 7 6 5 4 3 2 1 23 22 19 21 20 18

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

D0 D1 D2 D3 D4 D5 D6 D7

9 10 11 13 14 15 16 17

W G E 6116

Gambar 1.1 Susunan Kaki IC Memori 6116

Lab Teknik Digital

2

Jobsheet Praktikum D. Lembar Praktikum 1. Alat dan Bahan IC 6116

1 buah

IC 74245

1 buah

IC 74373

1 buah

Respack 10K Ω

2 buah

Resistor 10K Ω

2 buah

Resistor 220 Ω

8 buah

LED

8 buah

Push Button

2 buah

Dipwitch 8-bit

2 buah

Multimeter Digital

1 buah

Power Supply DC

1 buah

Project Board

1 buah

Pinset

1 buah

Jumper

secukupnya


Lab Teknik Digital

3

Jobsheet Praktikum

+5V

+5V

9

9 10 11 12 13 14 15 16

16 15 14 13 12 11 10

3. Langkah percobaan 7 1. Rakitlah rangkaian seperti Gambar 1.2 pada project board.

RESPACK3

RESPACK3 10k ohm

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9 +5V

SW-DIP8

8 7 6 5 4 3 2 1

1 2 3 4 5 6 7 8

10k ohm

8 7 6 5 4 3 2 1 23 22 19

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

20

D0 D1 D2 D3 D4 D5 D6 D7

A0 A1 A2 A3 A4 A5 A6 A7

18 17 16 15 14 13 12 11

B0 B1 B2 B3 B4 B5 B6 B7

16 15 14 13 12 11 10 9

E

1

DIR

74LS245 18 220 ohm

W

2 3 4 5 6 7 8 9

6116 READ +5V 10k WRITE

+5V 11 1

1D 2D 3D 4D 5D 6D 7D 8D

1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q

19 18 17 16 15 14 13 12

C OC 74HC573

Gambar 1.2 Rangkaian untuk Percobaan Memori 6116

2. Ukur catu daya DC sebesar +5V. Matikan catu daya dan hubungkan catu daya ke rangkaian.

Catatan: - LED nyala berarti logika 1 dan LED mati berarti logika 0. 3. Cek kondisi saklar, catat arah switch untuk menunjukkan logika 0 dan 1. 4. Hidupkan catu daya. 5. Set jalur alamat A10-A0 pada 00000000000 dan set jalur data D7-D0 pada 11111111. 6. Tekan saklar WRITE untuk memasukkan data ke dalam memori, kemudian lepaskan saklar. 7. Ulangi langkah 5 dan 6 untuk kombinasi alamat dan data yang lain seperti yang tertera dalam Tabel 1.1. 8. Set jalur alamat A10-A0 pada 00000000000. 9. Tekan saklar READ untuk membaca data pada memori, dan catat luaran LED dalam Tabel 1.1.

Lab Teknik Digital

1 2 3 4 5 6 7 8 SW-DIP8

E

21

2 3 4 5 6 7 8 9

19

G

10k

9 10 11 13 14 15 16 17

4

Jobsheet Praktikum

10. Ulangi langkah 8 dan 9 untuk kombinasi alamat yang lain seperti yang tertera dalam Tabel 1.1.

DATA HASIL PERCOBAAN Tabel 1.1 Data Hasil Percobaan IC Memori 6116 MASUKAN ALAMAT A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0 1 1 0 1

DATA D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1

LUARAN DATA D7 D6 D5 D4 D3 D2 D1 D0

TUGAS

1. Gambarkan blok diagram dan tabel kebenaran IC memori 6116. 2. * Kelompok 1 Susunlah sistem memori 4 kbyte dengan EPROM 1 kbyte. Buatlah pengalamatan (pendekodean) untuk setiap memori tersebut sehingga tidak ada alamat yang saling bertumpukan serta berilah penjelasan. * Kelompok 2 Susunlah sistem memori 16 kbyte dengan EPROM 4 kbyte. Buatlah pengalamatan (pendekodean) untuk setiap memori tersebut sehingga tidak ada alamat yang saling bertumpukan serta berilah penjelasan. * Kelompok 3 Susunlah sistem memori 32 kbyte dengan RAM statik 8 kbyte. Buatlah pengalamatan (pendekodean) untuk setiap memori tersebut sehingga tidak ada alamat yang saling bertumpukan serta berilah penjelasan.

Lab Teknik Digital

Jobsheet Praktikum

5

* Kelompok 4 Susunlah sistem memori 64 kbyte dengan EPROM 16 kbyte. Buatlah pengalamatan (pendekodean) untuk setiap memori tersebut sehingga tidak ada alamat yang saling bertumpukan serta berilah penjelasan. * Kelompok 5 Susunlah sistem memori 64 kbyte dengan RAM statik 32 kbyte. Buatlah pengalamatan (pendekodean) untuk setiap memori tersebut sehingga tidak ada alamat yang saling bertumpukan serta berilah penjelasan. * Kelompok 6 Susunlah sistem memori 16 kbyte dengan RAM statik 2 kbyte. Buatlah pengalamatan (pendekodean) untuk setiap memori tersebut sehingga tidak ada alamat yang saling bertumpukan serta berilah penjelasan.

Catatan: - Nama RAM/EPROM dapat dipilih sendiri asalkan kapasitasnya sesuai. - Range alamat ditentukan sendiri (dalam range 0000H – FFFFH).

Lab Teknik Digital

Jobsheet Praktikum

6

Analisa _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________

Lab Teknik Digital

Jobsheet Praktikum

7

Kesimpulan _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________

Lab Teknik Digital

1

Jobsheet Praktikum MULTIVIBRATOR

A. Tujuan Kegiatan Praktikum 8-9 : Setelah mempraktekkan Topik ini, anda diharapkan dapat : 1. Memahami macam-macam dan prinsip kerja multivibrator. 2.

Merancang timer/clock dan delay (aplikasi multivibrator) sesuai keperluan.

B. Dasar Teori Kegiatan Praktikum 8-9 Rangkaian multivibrator merupakan rangkaian yang digunakan untuk keperluan pewaktuan (timing) rangkaian elektronika. Multivibrator merupakan rangkaian yang berubah antara dua level digital secara kontinyu, berbasis “free running” atau berdasar permintaan dari sumber pemicu eksternal. Pada dasarnya ada 3 jenis multivibrator, yaitu: 1. Bistabil

: multivibrator yang dipicu ke salah satu dari 2 kondisi digital oleh sumber eksternal, dan berada dalam kondisi tersebut sampai dipicu ke kondisi sebaliknya.

2. Astabil

: osilator free running yang berkondisi antara 2 level digital pada frekuensi dan siklus kerja tertentu.

3. Monostabil

: dikenal sebagai one-shot, memberikan pulsa luaran tunggal pada lebar waktu tertentu ketika dipicu dari sumber eksternal.

Multivibrator dapat dibangun dari gerbang logika dasar, IC khusus yang dirancang untuk aplikasi pewaktuan (IC 555, IC 74121 atau 74123) ataupun osilator kristal. IC 555 adalah IC timer yang sangat populer dan banyak fungsinya. IC ini merupakan peranti yang kestabilannya tinggi untuk membangkitkan waktu tunda yang akurat (one-shot) atau osilator. Kaki tambahan digunakan untuk memicu atau me-reset jika diinginkan. Pada mode operasi waktu tunda, waktu tersebut dikontrol oleh satu resistor eksternal dan kapasitor. Untuk operasi astabil sebagai osilator, frekuensi free running dan siklus kerja dikontrol dengan dua kapasitor eksternal dan satu kapasitor. Rangkaian tersebut dapat dipicu atau di-reset pada tepi turun. Susunan kaki IC 555 dapat dilihat dalam Gambar 1.1.

Lab Teknik Digital

2

Jobsheet Praktikum 1 2 3 4

GND TRIG Q R

VCC DIS THR CVolt

8 7 6 5

555

Gambar 1.1 Susunan Kaki IC 555 D. Lembar Praktikum 1. Alat dan Bahan IC NE 555

1 buah

IC 7404

1 buah

Resistor 47K Ω

1 buah

Resistor 10K Ω

1 buah

Resistor 4K7 Ω

1 buah

Kapasitor 680 pF

1 buah

Kapasitor 0,01 µF

1 buah

Kapasitor 100 µF

1 buah

Project Board

1 buah

Pinset

1 buah

Function Generator

1 buah

Osiloskop

1 buah

Frekuensi Counter

1 buah

Multimeter Digital

1 buah

Power Supply DC

1 buah

Jumper

secukupnya


Lab Teknik Digital

3

Jobsheet Praktikum 3. Langkah percobaan 8 1. Rakitlah rangkaian seperti Gambar 1.2 pada project board. VCC=5V

8

4

RA 4,7 k

THR

VCC

Vou t

55 5

5

C 68 0 pF

3

Q

CVolt

6

TRIG

GND

2

DIS

1

RB 10 k

R

U1 7

0,01 u F

Gambar 1.2 Rangkaian untuk Percobaan Multivibrator Astabil

2. Ukur catu daya DC sebesar +5V. Matikan catu daya dan hubungkan ke rangkaian. 3. Hidupkan catu daya, osiloskop dan frequency counter. 4. Hubungkan probe osiloskop dan probe frequency counter ke Vout. 5. Set volt/div dan time/div sehingga diperoleh gambar yang jelas. 6. Gambar sinyal luaran tersebut beserta volt/div dan time/div dan catat tampilan frekuensi pada frequency counter.

DATA HASIL PERCOBAAN

Lab Teknik Digital

Jobsheet Praktikum ANALISIS Hasil Perhitungan Secara Teori Waktu pengisian (luaran HIGH): t HI  0,693 (R A  R B ) C 

Waktu pengosongan (luaran LOW): t LO  0,693 (R B ) C 

Periode total: T  t HI  t LO  0,693 (R A  2R B ) C 

Frekuensi osilasi: f

1 1,44   T (R A  2R B ) C

Siklus kerja (duty cycle): D

RB  R A  2R B

Hasil Pengukuran dari Osiloskop dan Frequency Counter Waktu pengisian (luaran HIGH): t HI 

Waktu pengosongan (luaran LOW): t LO 

Frekuensi osilasi: f 

Periode total: T

1  f

Siklus kerja (duty cycle): D

t HI  t HI  t LO

Lab Teknik Digital

4

Jobsheet Praktikum

5

Tugas: 1. Menggunakan 555 rancang multivibrator astabil yang berosilasi pada 50 kHz dengan siklus kerja 60%. Ambil nilai C = 0,0022 F. 2. Berikan contoh salah satu aplikasi multivibrator astabil dalam rangkaian elektronika digital.

Lab Teknik Digital

6

Jobsheet Praktikum 4. Langkah Percobaan 9 1. Rakitlah rangkaian seperti Gambar 1.3 pada project board.

8

4

VCC = 5V

U2

THR

2

DIS

6 7

Q

C 100 pF

3

5

GND

1

555

TRIG

CVolt

Vin

RA 47k

R VCC

10 k

0,01 uF 1

U3A SN74LS04 2

Vout

Gambar 1.3 Rangkaian untuk Percobaan Multivibrator Monostabil

2. Ukur catu daya DC sebesar +5V. Matikan catu daya dan hubungkan ke rangkaian. 3. Ukur frekuensi pada function generator sebesar 10 kHz dan hubungkan ke Vin pada rangkaian. 4. Hidupkan catu daya, function generator, osiloskop dan frequency counter. 5. Hubungkan 2 probe osiloskop ke Vin dan Vout, serta probe frequency counter bergantian ke Vin dan Vout. 6. Set volt/div dan time/div sehingga diperoleh gambar yang jelas. Gambar sinyal Vin dan Vout beserta volt/div dan time/div dan catat tampilan frekuensi pada frequency counter untuk keduanya.

DATA HASIL PERCOBAAN

Lab Teknik Digital

Jobsheet Praktikum ANALISIS Hasil Perhitungan Secara Teori Frekuensi osilasi Vin dan Vout: f 

Lebar pulsa yang diinginkan pada Vout: t W  1,1 (R A ) C 

Hasil Pengukuran dari Osiloskop dan Frequency Counter Untuk Vin: Waktu HIGH: t HI 

Waktu LOW: t LO 


Periode total: T

1  f

Untuk Vout: Waktu HIGH: t HI 

Waktu LOW: t LO  t W 


Periode total: T

1  f

Lab Teknik Digital

7

Jobsheet Praktikum

8

Tabel 1.1 Perbandingan Hasil Perhitungan dengan Pengukuran Vin Vout Teori (Perhitungan) Praktek (Pengukuran) Teori (Perhitungan) Praktek (Pengukuran) tHI tLO (tW) T f

TUGAS 1. Rancang rangkaian one-shot dengan IC 555 agar mengeluarkan sinyal dengan waktu HIGH 10 s setiap periode 60 s. Asumsikan Vin mempunyai waktu LOW selama 1 s setiap periode 60 s dan Vcc yang digunakan sebesar 5V. Gambarkan bentuk gelombang Vin dan Vout untuk rangkaian tersebut. 2. Rancanglah multivibrator monostabil dengan IC 74121 yang mengonversi gelombang kotak 100 kHz, siklus kerja 30% menjadi gelombang kotak 100 kHz, siklus kerja 50%. 3. Beri contoh aplikasi multivibrator monostabil dalam rangkaian elektronika digital.

Lab Teknik Digital

Jobsheet Praktikum

9

Data Hasil Percobaan _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________

Lab Teknik Digital

Jobsheet Praktikum

10

Analisa _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________

Lab Teknik Digital

Jobsheet Praktikum

11

Kesimpulan _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________

Lab Teknik Digital

SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

D Dependable Texas Instruments Quality and Reliability

description/ordering information

SN5404 . . . J PACKAGE SN54LS04, SN54S04 . . . J OR W PACKAGE SN7404, SN74S04 . . . D, N, OR NS PACKAGE SN74LS04 . . . D, DB, N, OR NS PACKAGE (TOP VIEW)

1A 1Y 2A 2Y 3A 3Y GND

These devices contain six independent inverters.

1

14

2

13

3

12

4

11

5

10

6

9

7

8

VCC 6A 6Y 5A 5Y 4A 4Y

SN5404 . . . W PACKAGE (TOP VIEW)

1A 2Y 2A

1

14

2

13

3

12

VCC 3A 3Y 4A

4

11

5

10

6

9

7

8

1Y 6A 6Y GND 5Y 5A 4Y

1Y 1A NC VCC 6A

SN54LS04, SN54S04 . . . FK PACKAGE (TOP VIEW)

4

3 2 1 20 19 18

5

17

6

16

7

15

8

14 9 10 11 12 13

6Y NC 5A NC 5Y

3Y GND NC 4Y 4A

2A NC 2Y NC 3A

NC − No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated

!" #!$% &"' &! #" #" (" " ") !" && *+' &! #", &" ""%+ %!&" ", %% #""'

#&! #% - ./.010 %% #"" " ""& !%" ("*" "&' %% (" #&! #&! #", &" ""%+ %!&" ", %% #""'

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

1


ORDERING INFORMATION

PDIP − N

0°C 0 C to 70 70°C C

ORDERABLE PART NUMBER

PACKAGE†

TA

SOIC − D

SOP − NS SSOP − DB

CDIP − J

−55°C −55 C to 125 125°C C CFP − W

LCCC − FK

TOP-SIDE MARKING

Tube

SN7404N

SN7404N

Tube

SN74LS04N

SN74LS04N

Tube

SN74S04N

SN74S04N

Tube

SN7404D

Tape and reel

SN7404DR

Tube

SN74LS04D

Tape and reel

SN74LS04DR

Tube

SN74S04D

Tape and reel

SN74S04DR

Tape and reel

SN7404NSR

SN7404

Tape and reel

SN74LS04NSR

74LS04

Tape and reel

SN74S04NSR

74S04

Tape and reel

SN74LS04DBR

LS04

Tube

SN5404J

SN5404J

Tube

SNJ5404J

SNJ5404J

Tube

SN54LS04J

SN54LS04J

Tube

SN54S04J

SN54S04J

Tube

SNJ54LS04J

SNJ54LS04J

Tube

SNJ54S04J

SNJ54S04J

Tube

SNJ5404W

SNJ5404W

Tube

SNJ54LS04W

SNJ54LS04W

Tube

SNJ54S04W

SNJ54S04W

Tube

SNJ54LS04FK

SNJ54LS04FK

Tube

SNJ54S04FK

SNJ54S04FK

7404 LS04 S04

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each inverter)

2

INPUT A

OUTPUT Y

H

L

L

H




logic diagram (positive logic) 1A

1Y

2A

2Y

3A

3Y

4A

4Y

5A

5Y

6A

6Y

Y=A



3


schematics (each gate) ’04 VCC

4 kΩ

130 Ω

1.6 kΩ

Input A Output Y

1 kΩ GND

’LS04

’S04 VCC

20 kΩ

120 Ω

8 kΩ

Input A

VCC

4 kΩ

2.8 kΩ

Output Y

50 Ω

900 Ω

Input A

3.5 kΩ

Output Y

12 kΩ 500 Ω

250 Ω

3 kΩ 1.5 kΩ

GND GND

Resistor values shown are nominal.

4




absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI: ’04, ’S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V ’LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3) SN7404

SN5404 VCC VIH

Supply voltage

VIL IOH

Low-level input voltage

IOL TA

Low-level output current

High-level input voltage

MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

2

2

High-level output current −55

V V

0.8

0.8

V

−0.4

−0.4

mA

16

mA

70

°C

16

Operating free-air temperature

UNIT

125

0

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS‡

PARAMETER VIK VOH

VCC = MIN, VCC = MIN,

II = − 12 mA VIL = 0.8 V,

VOL II

VCC = MIN, VCC = MAX,

VIH = 2 V, VI = 5.5 V

IIH IIL

VCC = MAX, VCC = MAX,

VI = 2.4 V VI = 0.4 V

IOS¶ ICCH

VCC = MAX

ICCL


MIN

SN5404 TYP§

MAX

MIN

SN7404 TYP§

−1.5 IOH = −0.4 mA IOL = 16 mA

2.4

3.4 0.2

−1.5 2.4

0.4

3.4 0.2

1

−20 VI = 0 V VI = 4.5 V

MAX

UNIT V V

0.4 1

V mA

40

40

µA

−1.6

−1.6

mA

−55

mA

−55

−18

6

12

6

12

mA

18

33

18

33

mA

‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § All typical values are at VCC = 5 V, TA = 25°C. ¶ Not more than one output should be shorted at a time.



5


switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) PARAMETER tPLH tPHL

FROM (INPUT)

TO (OUTPUT)

A

Y

SN5404 SN7404

TEST CONDITIONS MIN RL = 400 Ω,

CL = 15 pF

UNIT

TYP

MAX

12

22

8

15

ns

recommended operating conditions (see Note 3) SN74LS04

SN54LS04 VCC VIH

Supply voltage

VIL IOH


IOL TA


MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

2

2

UNIT V V

0.7

0.8

V

High-level output current

−0.4

−0.4

mA


4

8

mA

70

°C


−55

125

0


electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

VIK VOH

SN54LS04 MIN TYP‡ MAX

TEST CONDITIONS†

PARAMETER VCC = MIN, VCC = MIN,

II = − 18 mA VIL = MAX,

SN74LS04 MIN TYP‡ MAX

−1.5 IOH = −0.4 mA IOL = 4 mA

2.5

3.4 0.25

−1.5 2.7

3.4

0.4

UNIT V V

0.4

VOL

VCC = MIN,

VIH = 2 V

II IIH


VI = 7 V VI = 2.7 V

0.1

0.1

20

20

µA

IIL IOS§

VCC = MAX, VCC = MAX

VI = 0.4 V

−0.4

−0.4

mA

ICCH ICCL


VI = 0 V VI = 4.5 V

IOL = 8 mA

0.25

−20

−100

−20

0.5

V mA

−100

mA

1.2

2.4

1.2

2.4

mA

3.6

6.6

3.6

6.6

mA

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2) PARAMETER tPLH tPHL

6

FROM (INPUT)

TO (OUTPUT)

A

Y

TEST CONDITIONS

SN54LS04 SN74LS04 MIN

RL = 2 kΩ,


CL = 15 pF


UNIT

TYP

MAX

9

15

10

15

ns


recommended operating conditions (see Note 3) SN74S04

SN54S04 MIN

NOM

MAX

MIN

NOM

MAX

4.5

5

5.5

4.75

5

5.25

UNIT

VCC VIH

Supply voltage

VIL IOH


0.8

0.8

V

High-level output current

−1

−1

mA

IOL TA


20

mA

70

°C


2

2

V

20


−55

125

V

0


electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS†

PARAMETER VIK VOH

VCC = MIN, VCC = MIN,

II = − 18 mA VIL = 0.8 V,

VOL II

VCC = MIN, VCC = MAX,

VIH = 2 V, VI = 5.5 V

IIH IIL


VI = 2.7 V VI = 0.5 V

IOS§ ICCH

VCC = MAX

ICCL


MIN

SN54S04 TYP‡ MAX

MIN

SN74S04 TYP‡ MAX

−1.2 IOH = −1 mA IOL = 20 mA

2.5

3.4

−40 VI = 0 V VI = 4.5 V

−1.2 2.7

3.4

UNIT V V

0.5

0.5

1

1

V mA

50

50

µA

−2

−2

mA

−100

mA

−100

−40

15

24

15

24

mA

30

54

30

54

mA

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1) FROM (INPUT)

TO (OUTPUT)

tPLH tPHL

A

Y

RL = 280 Ω,

CL = 15 pF

tPLH tPHL

A

Y

RL = 280 Ω,

CL = 50 pF

PARAMETER

SN54S04 SN74S04

TEST CONDITIONS MIN



UNIT

TYP

MAX

3

4.5

3

5

4.5 5

ns ns

7


PARAMETER MEASUREMENT INFORMATION SERIES 54/74 AND 54S/74S DEVICES VCC Test Point

VCC

RL (see Note B)

From Output Under Test CL (see Note A)

High-Level Pulse

1.5 V

S2

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V

Timing Input

1.5 V

1 kΩ

Test Point

LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS

S1 (see Note B)

CL (see Note A)

RL

CL (see Note A)

RL

From Output Under Test

VCC


Test Point

1.5 V 0V

tw Low-Level Pulse

1.5 V

tsu Data Input

1.5 V

VOLTAGE WAVEFORMS PULSE DURATIONS

1.5 V

1.5 V

In-Phase Output (see Note D)

tPHL VOH 1.5 V

Out-of-Phase Output (see Note D)

0V

1.5 V

1.5 V

Waveform 1 (see Notes C and D)

tPLZ

VOH 1.5 V

1.5 V VOL

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

≈1.5 V

1.5 V VOL tPZH

tPLH

1.5 V 0V

tPZL

VOL

tPHL

1.5 V

3V

Output Control (low-level enabling)

0V tPLH

3V 1.5 V

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

3V Input

th


VOL + 0.5 V

tPHZ VOH 1.5 V

VOH − 0.5 V ≈1.5 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time, with one input transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

8




PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES VCC Test Point

VCC

RL

From Output Under Test CL (see Note A)

CL (see Note A)

High-Level Pulse

1.3 V

S2

LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V

Timing Input

1.3 V

5 kΩ

Test Point

LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS

S1 (see Note B)

CL (see Note A)

RL (see Note B)

RL


VCC


Test Point

1.3 V 0V

tw Low-Level Pulse

1.3 V

tsu

0V

In-Phase Output (see Note D)

3V 1.3 V

1.3 V 0V

tPZL

tPLZ

tPHL VOH 1.3 V

1.3 V


VOL tPZH

tPLH VOH 1.3 V

1.3 V VOL


VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

≈1.5 V

1.3 V

VOL

tPHL Out-of-Phase Output (see Note D)

1.3 V 0V

Output Control (low-level enabling)

1.3 V

tPLH

1.3 V

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

3V 1.3 V

3V

Data Input

1.3 V

VOLTAGE WAVEFORMS PULSE DURATIONS

Input

th

VOL + 0.5 V

tPHZ VOH 1.3 V

VOH − 0.5 V ≈1.5 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time, with one input transition per measurement.

Figure 2. Load Circuits and Voltage Waveforms



9

PACKAGE OPTION ADDENDUM

www.ti.com

17-Dec-2015

PACKAGING INFORMATION Orderable Device

Status (1)

Package Type Package Pins Package Drawing Qty

Eco Plan

Lead/Ball Finish

MSL Peak Temp

(2)

(6)

(3)

Op Temp (°C)

Device Marking (4/5)

JM38510/00105BCA

ACTIVE

CDIP

J

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

JM38510/ 00105BCA

JM38510/00105BDA

ACTIVE

CFP

W

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

JM38510/ 00105BDA

JM38510/07003BCA

ACTIVE

CDIP

J

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

JM38510/ 07003BCA

JM38510/07003BDA

ACTIVE

CFP

W

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

JM38510/ 07003BDA

JM38510/30003B2A

ACTIVE

LCCC

FK

20

1

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

JM38510/ 30003B2A

JM38510/30003BCA

ACTIVE

CDIP

J

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

JM38510/ 30003BCA

JM38510/30003BDA

ACTIVE

CFP

W

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

JM38510/ 30003BDA

JM38510/30003SCA

ACTIVE

CDIP

J

14

25

TBD

A42

N / A for Pkg Type

-55 to 125

JM38510/ 30003SCA

M38510/00105BCA

ACTIVE

CDIP

J

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

JM38510/ 00105BCA

M38510/00105BDA

ACTIVE

CFP

W

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

JM38510/ 00105BDA

M38510/07003BCA

ACTIVE

CDIP

J

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

JM38510/ 07003BCA

M38510/07003BDA

ACTIVE

CFP

W

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

JM38510/ 07003BDA

M38510/30003B2A

ACTIVE

LCCC

FK

20

1

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

JM38510/ 30003B2A

M38510/30003BCA

ACTIVE

CDIP

J

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

JM38510/ 30003BCA

M38510/30003BDA

ACTIVE

CFP

W

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

JM38510/ 30003BDA

M38510/30003SCA

ACTIVE

CDIP

J

14

25

TBD

A42

N / A for Pkg Type

-55 to 125

JM38510/ 30003SCA

SN5404J

ACTIVE

CDIP

J

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

SN5404J

Addendum-Page 1

Samples


www.ti.com

17-Dec-2015

Orderable Device

Status (1)


Eco Plan

Lead/Ball Finish

MSL Peak Temp

(2)

(6)

(3)

Op Temp (°C)


SN54LS04J

ACTIVE

CDIP

J

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

SN54LS04J

SN54S04J

ACTIVE

CDIP

J

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

SN54S04J

SN7404D

ACTIVE

SOIC

D

14

50

Green (RoHS & no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

7404

SN7404DE4

ACTIVE

SOIC

D

14

50


CU NIPDAU

Level-1-260C-UNLIM

0 to 70

7404

SN7404DG4

ACTIVE

SOIC

D

14

50


CU NIPDAU

Level-1-260C-UNLIM

0 to 70

7404

SN7404DR

ACTIVE

SOIC

D

14

2500


CU NIPDAU

Level-1-260C-UNLIM

0 to 70

7404

SN7404N

ACTIVE

PDIP

N

14

25

Pb-Free (RoHS)

CU NIPDAU

N / A for Pkg Type

0 to 70

SN7404N

SN7404N3

OBSOLETE

PDIP

N

14

TBD

Call TI

Call TI

0 to 70

SN7404NE4

ACTIVE

PDIP

N

14

25

Pb-Free (RoHS)

CU NIPDAU

N / A for Pkg Type

0 to 70

SN7404N

SN74LS04D

ACTIVE

SOIC

D

14

50


CU NIPDAU

Level-1-260C-UNLIM

0 to 70

LS04

SN74LS04DBR

ACTIVE

SSOP

DB

14

2000


CU NIPDAU

Level-1-260C-UNLIM

SN74LS04DG4

ACTIVE

SOIC

D

14

50


CU NIPDAU

Level-1-260C-UNLIM

0 to 70

LS04

SN74LS04DR

ACTIVE

SOIC

D

14

2500


CU NIPDAU

Level-1-260C-UNLIM

0 to 70

LS04

SN74LS04DRE4

ACTIVE

SOIC

D

14

2500


CU NIPDAU

Level-1-260C-UNLIM

0 to 70

LS04

SN74LS04DRG4

ACTIVE

SOIC

D

14

2500


CU NIPDAU

Level-1-260C-UNLIM

0 to 70

LS04

SN74LS04J

OBSOLETE

CDIP

J

14

TBD

Call TI

Call TI

0 to 70

SN74LS04N

ACTIVE

PDIP

N

14

25

Pb-Free (RoHS)

CU NIPDAU

N / A for Pkg Type

0 to 70

SN74LS04N3

OBSOLETE

PDIP

N

14

TBD

Call TI

Call TI

0 to 70

SN74LS04NE4

ACTIVE

PDIP

N

14

25

Pb-Free (RoHS)

CU NIPDAU

N / A for Pkg Type

0 to 70

Addendum-Page 2

LS04

SN74LS04N

SN74LS04N

Samples


www.ti.com

17-Dec-2015

Orderable Device

Status (1)


Eco Plan

Lead/Ball Finish

MSL Peak Temp

(2)

(6)

(3)

Op Temp (°C)


SN74LS04NSR

ACTIVE

SO

NS

14

2000


CU NIPDAU

Level-1-260C-UNLIM

0 to 70

74LS04

SN74LS04NSRG4

ACTIVE

SO

NS

14

2000


CU NIPDAU

Level-1-260C-UNLIM

0 to 70

74LS04

SN74S04D

ACTIVE

SOIC

D

14

50


CU NIPDAU

Level-1-260C-UNLIM

0 to 70

S04

SN74S04DG4

ACTIVE

SOIC

D

14

50


CU NIPDAU

Level-1-260C-UNLIM

0 to 70

S04

SN74S04DR

ACTIVE

SOIC

D

14

2500


CU NIPDAU

Level-1-260C-UNLIM

0 to 70

S04

SN74S04N

ACTIVE

PDIP

N

14

25

Pb-Free (RoHS)

CU NIPDAU

N / A for Pkg Type

0 to 70

SN74S04N

SN74S04N3

OBSOLETE

PDIP

N

14

TBD

Call TI

Call TI

0 to 70

SN74S04NE4

ACTIVE

PDIP

N

14

25

Pb-Free (RoHS)

CU NIPDAU

N / A for Pkg Type

0 to 70

SN74S04N

SN74S04NSR

ACTIVE

SO

NS

14

2000


CU NIPDAU

Level-1-260C-UNLIM

0 to 70

74S04

SNJ5404J

ACTIVE

CDIP

J

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

SNJ5404J

SNJ5404W

ACTIVE

CFP

W

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

SNJ5404W

SNJ54LS04FK

ACTIVE

LCCC

FK

20

1

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

SNJ54LS 04FK

SNJ54LS04J

ACTIVE

CDIP

J

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

SNJ54LS04J

SNJ54LS04W

ACTIVE

CFP

W

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

SNJ54LS04W

SNJ54S04FK

ACTIVE

LCCC

FK

20

1

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

SNJ54S 04FK

SNJ54S04J

ACTIVE

CDIP

J

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

SNJ54S04J

SNJ54S04W

ACTIVE

CFP

W

14

1

TBD

A42

N / A for Pkg Type

-55 to 125

SNJ54S04W

(1)

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

Addendum-Page 3

Samples


www.ti.com

17-Dec-2015

OBSOLETE: TI has discontinued the production of the device. (2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN5404, SN54LS04, SN54LS04-SP, SN54S04, SN7404, SN74LS04, SN74S04 :

• Catalog: SN7404, SN74LS04, SN54LS04, SN74S04 • Military: SN5404, SN54LS04, SN54S04 • Space: SN54LS04-SP NOTE: Qualified Version Definitions:

Addendum-Page 4


www.ti.com

17-Dec-2015

• Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 5

PACKAGE MATERIALS INFORMATION www.ti.com

10-Sep-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins Type Drawing

SPQ

Reel Reel A0 Diameter Width (mm) (mm) W1 (mm)

B0 (mm)

K0 (mm)

P1 (mm)

W Pin1 (mm) Quadrant

SN7404DR

SOIC

D

14

2500

330.0

16.4

6.5

9.0

2.1

8.0

16.0

Q1

SN74LS04DBR

SSOP

DB

14

2000

330.0

16.4

8.2

6.6

2.5

12.0

16.0

Q1

SN74LS04DR

SOIC

D

14

2500

330.0

16.4

6.5

9.0

2.1

8.0

16.0

Q1

SN74S04DR

SOIC

D

14

2500

330.0

16.4

6.5

9.0

2.1

8.0

16.0

Q1

SN74S04NSR

SO

NS

14

2000

330.0

16.4

8.2

10.5

2.5

12.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com

10-Sep-2015

*All dimensions are nominal

Device

Package Type

Package Drawing

Pins

SPQ

Length (mm)

Width (mm)

Height (mm)

SN7404DR

SOIC

D

14

2500

367.0

367.0

38.0

SN74LS04DBR

SSOP

DB

14

2000

367.0

367.0

38.0

SN74LS04DR

SOIC

D

14

2500

367.0

367.0

38.0

SN74S04DR

SOIC

D

14

2500

367.0

367.0

38.0

SN74S04NSR

SO

NS

14

2000

367.0

367.0

38.0

Pack Materials-Page 2

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN 0,38 0,22

0,65 28

0,15 M

15

0,25 0,09 8,20 7,40

5,60 5,00

Gage Plane 1

14

0,25

A

0°–ā8°

0,95 0,55

Seating Plane 2,00 MAX

0,10

0,05 MIN

PINS **

14

16

20

24

28

30

38

A MAX

6,50

6,50

7,50

8,50

10,50

10,50

12,90

A MIN

5,90

5,90

6,90

7,90

9,90

9,90

12,30

DIM

4040065 /E 12/01 NOTES: A. B. C. D.

All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150



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Copyright  1998, Texas Instruments Incorporated

M54HC164 M74HC164 8 BIT SIPO SHIFT REGISTER

. . . . . . . .

HIGH SPEED tPD = 15 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS BALANCED PROPAGATION DELAYS tPLH = tPHL SYMMETRICAL OUTPUT IMPEDANCE IOL = IOH = 4 mA (MIN.) HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS164

B1R (Plastic Package)

F1R (Ceramic Package)

M1R (Micro Package)

C1R (Chip Carrier)

ORDER CODES : M54HC164F1R M74HC164M1R M74HC164B1R M74HC164C1R

PIN CONNECTIONS (top view)

DESCRIPTION The M54/74HC164 is a high speed CMOS 8 BIT SIPO SHIFT REGISTER fabricated in silicon gate 2 C MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The HC164 is an 8 bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B), either of these inputs can be used as an active high enable for data entry through the other input. An unused input must be high, or both inputs connected together. Each low-to-high transition on the clock input shifts data one place to the right and enters into QA, the logic NAND of the two data inputs (A ⋅ B), the data that existed before the rising clock edge. A low level on the clear input overrides all other inputs and clears the register asynchronously, forcing all Q outputs low. All inputs are equipped with protection circuits against static discharge and transient excess voltage. October 1992

NC = No Internal Connection

1/12

M54/M74HC164 INPUT AND OUTPUT EQUIVALENT CIRCUIT

TRUTH TABLE INPUTS CLEAR

CLOCK

L

X

OUTPUS SERIAL IN

QA

QB

............

QH

L

L

............

L

X L

L L

QAn QAn

............

QGn QGn

H

H

QAn

............

QGn

A X

B X

H

X

X

H H

L X

H

H

X: Don’t Care QAn - QGn : The level of QA -QG, respectively. before the most-recent transition of th clock.

LOGIC DIAGRAM

2/12

NO CHANGE ............

M54/M74HC164 PIN DESCRIPTION

IEC LOGIC SYMBOL

PIN No

SYMBOL

NAME AND FUNCTION

1, 2 3, 4, 5, 6, 10, 11, 12, 13 8

A, B QA to QH

Data Inputs Outputs

CLOCK

Clock Input (LOW to HIGH, Edge-triggered)

9

CLEAR

Master Reset Input

7 14

GND V CC

Ground (0V) Positive Supply Voltage

ABSOLUTE MAXIMUM RATINGS Symbol VCC

Parameter Supply Voltage

Value -0.5 to +7

Unit V

VI

DC Input Voltage

-0.5 to VCC + 0.5

V

VO IIK

DC Output Voltage DC Input Diode Current

-0.5 to VCC + 0.5 ± 20

V mA

IOK

DC Output Diode Current

± 20

mA

DC Output Source Sink Current Per Output Pin DC VCC or Ground Current

± 25 ± 50

mA mA

500 (*)

mW

IO ICC or IGND PD

Power Dissipation

Tstg TL

Storage Temperature Lead Temperature (10 sec)

-65 to +150 300

o o

C C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied. (*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC

RECOMMENDED OPERATING CONDITIONS Symbol VCC

Parameter Supply Voltage

VI

Input Voltage

VO Top

Output Voltage Operating Temperature: M54HC Series M74HC Series

tr, tf

Input Rise and Fall Time

Value 2 to 6

Unit V

0 to VCC

V

0 to VCC -55 to +125 -40 to +85 VCC = 2 V

0 to 1000

VCC = 4.5 V VCC = 6 V

0 to 500 0 to 400

V C o C o

ns

3/12

M54/M74HC164 DC SPECIFICATIONS Test Conditions Symbol

VIH

V IL

Parameter

High Level Input Voltage Low Level Input Voltage

Value

VCC (V)

TA = 25 oC 54HC and 74HC Min. Typ. Max.

2.0

1.5

1.5

1.5

4.5 6.0

3.15 4.2

3.15 4.2

3.15 4.2

High Level Output Voltage

0.5

0.5

0.5

4.5

1.35

1.35

1.35

2.0 4.5 6.0 4.5

VOL

Low Level Output Voltage

6.0 2.0 4.5 6.0 4.5 6.0

II ICC

4/12

Input Leakage Current Quiescent Supply Current

6.0 6.0

1.8

1.8

Unit

V

2.0 6.0

V OH

-40 to 85 oC -55 to 125 oC 74HC 54HC Min. Max. Min. Max.

V

1.8

1.9

2.0

1.9

1.9

VI = IO=-20 µA VIH or V IL IO=-4.0 mA

4.4 5.9

4.5 6.0

4.4 5.9

4.4 5.9

4.18

4.31

4.13

4.10

IO=-5.2 mA

5.68

5.8 0.0

5.63

5.60

V

VI = IO= 20 µA VIH or V IL IO= 4.0 mA

0.1

0.1

0.1

0.0

0.1

0.1

0.1

0.0 0.17

0.1 0.26

0.1 0.33

0.1 0.40

IO= 5.2 mA

0.18

V

0.26

0.33

0.40

VI = VCC or GND

±0.1

±1

±1

µA

VI = VCC or GND

4

40

80

µA

M54/M74HC164 AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns) Test Conditions o

TA = 25 C 54HC and 74HC

Value -40 to 85 oC -55 to 125 oC 74HC 54HC

Symbol

Parameter

VCC (V)

tTLH tTHL

Output Transition Time

2.0 4.5

Typ. 30 8

Max. 75 15

tPLH tPHL

Propagation Delay Time (CLOCK - Q)

6.0 2.0 4.5 6.0

7 57 19 16

13 160 32 27

16 200 40 34

19 240 48 41

ns

tPHL

Propagation Delay Time (CLEAR - Q)

2.0 4.5 6.0 2.0 4.5

60 20 17 18 53

175 35 30

220 44 37

265 53 45

ns

fMAX

Maximum Clock Frequency

tW(H) tW(L)

Minimum Pulse Width (CLOCK)

6.0 2.0 4.5 6.0

tW(L)

Minimum Pulse Width (CLEAR) Minimum Set-up Time (A, B - CK)

ts

th

tREM

CIN CPD (*)

Minimum Hold Time (A, B - CK) Minimum Removal Time Input Capacitance Power Dissipation Capacitance

Min.

6.2 31 37

Min.

Max. 95 19

5.0 25

Min.

Max. 110 22

4.2 21

ns

MHz

62 24 6 5

75 15 13

95 19 16

110 22 19

ns

2.0 4.5 6.0

40 10 9

75 15 13

95 19 16

110 22 19

ns

2.0 4.5

16 4

50 10

65 13

75 15

ns

6.0 2.0

3

9 5

11 5

13 5

4.5 6.0

5 5

5 5

5 5

2.0 4.5 6.0

5 5 5

5 5 5

5 5 5

ns

10

10

10

pF

5 99

30

Unit

25

ns

pF

(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC

5/12

M54/M74HC164 TIMING CHART

6/12

M54/M74HC164 SWITCHING CHARACTERISTICS TEST WAVEFORM CLEAR MODE

SERIAL MODE

TEST CIRCUIT ICC (Opr.)

INPUT WAVEFORM IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICS TEST.

7/12

M54/M74HC164

Plastic DIP14 MECHANICAL DATA mm

DIM. MIN. a1

0.51

B

1.39

TYP.

inch MAX.

MIN.

TYP.

MAX.

0.020 1.65

0.055

0.065

b

0.5

0.020

b1

0.25

0.010

D

20

0.787

E

8.5

0.335

e

2.54

0.100

e3

15.24

0.600

F

7.1

0.280

I

5.1

0.201

L Z

3.3 1.27

0.130 2.54

0.050

0.100

P001A

8/12

M54/M74HC164

Ceramic DIP14/1 MECHANICAL DATA mm

DIM. MIN.

TYP.

inch MAX.

MIN.

TYP.

MAX.

A

20

0.787

B

7.0

0.276

D E

3.3

0.130

0.38

e3

0.015 15.24

0.600

F

2.29

2.79

0.090

0.110

G

0.4

0.55

0.016

0.022

H

1.17

1.52

0.046

0.060

L

0.22

0.31

0.009

0.012

M

1.52

2.54

0.060

0.100

N P Q

10.3 7.8

8.05 5.08

0.406 0.307

0.317 0.200

P053C

9/12

M54/M74HC164

SO14 MECHANICAL DATA mm

DIM. MIN.

TYP.

A a1

inch MAX.

MIN.

TYP.

1.75 0.1

0.068

0.2

a2

MAX.

0.003

0.007

1.65

0.064

b

0.35

0.46

0.013

0.018

b1

0.19

0.25

0.007

0.010

C

0.5

0.019

c1

45° (typ.)

D

8.55

E

5.8

8.75

0.336

6.2

0.228

0.344 0.244

e

1.27

0.050

e3

7.62

0.300

F

3.8

4.0

0.149

0.157

G

4.6

5.3

0.181

0.208

L

0.5

1.27

0.019

0.050

M S

0.68

0.026 8° (max.)

P013G

10/12

M54/M74HC164

PLCC20 MECHANICAL DATA mm

DIM. MIN.

TYP.

inch MAX.

MIN.

TYP.

MAX.

A

9.78

10.03

0.385

0.395

B

8.89

9.04

0.350

0.356

D

4.2

4.57

0.165

0.180

d1

2.54

0.100

d2

0.56

0.022

E

7.37

8.38

0.290

0.330

e

1.27

0.050

e3

5.08

0.200

F

0.38

0.015

G

0.101

0.004

M

1.27

0.050

M1

1.14

0.045

P027A

11/12

M54/M74HC164

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics.  1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A

12/12

DM74LS165 8-Bit Parallel In/Serial Output Shift Registers

August 1986 Revised March 2000

DM74LS165 8-Bit Parallel In/Serial Output Shift Registers General Description

Features

This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit.

■ Complementary outputs

Clocking is accomplished through a 2-input NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking, and holding either clock input LOW with the load input HIGH enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is HIGH. Parallel loading is inhibited as long as the load input is HIGH. Data at the parallel inputs are loaded directly into the register on a HIGH-to-LOW transition of the shift/load input, regardless of the logic levels on the clock, clock inhibit, or serial inputs.

■ Typical power dissipation 105 mW

■ Direct overriding (data) inputs ■ Gated clock inputs ■ Parallel-to-serial data conversion ■ Typical frequency 35 MHz

Ordering Code: Order Number

Package Number

Package Description

DM74LS165M

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

DM74LS165WM

M16B

16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

DM74LS165N

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table Inputs

Internal

Shift/ Clock Clock Serial Parallel Outputs Output A...H

QA

QB

L

X

X

X

a...h

a

b

H

L

L

X

X

H

L

↑

H

X

H

QAn

QGn

H

L

↑

L

X

L

QAn

QGn

H

H

X

X

X

QA0 QB0

QH0

Load Inhibit

QA0 QB0

QH h QH0

H = HIGH Level (steady state) L = LOW Level (steady state) X = Don't Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level a...h = The level of steady-state input at inputs A through H, respectively. QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn = The level of QA or QG, respectively, before the most recent ↑ transition of the clock.

© 2000 Fairchild Semiconductor Corporation

DS006399

www.fairchildsemi.com

DM74LS165

Logic Diagram

Timing Diagram

Typical Shift, Load, and Inhibit Sequences


2

Supply Voltage

Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

7V

Input Voltage

7V 0°C to +70°C

Operating Free Air Temperature Range

−65°C to +150°C

Storage Temperature Range

Recommended Operating Conditions Symbol

Parameter

Min

Nom

Max

4.75

5

5.25

Units

VCC

Supply Voltage

VIH

HIGH Level Input Voltage

VIL

LOW Level Input Voltage

0.8

V

IOH

HIGH Level Output Current

−0.4

mA

IOL

LOW Level Output Current

fCLK

Clock Frequency (Note 2)

fCLK

Clock Frequency (Note 3)

tW

Pulse Width

Clock

25

(Note 3)

Load

15

tSU

V

2

V

8

mA

0

25

MHz

0

20

MHz

Setup Time

Parallel

10

(Note 4)

Serial

20

Enable

30

Shift

45

tH

Hold Time (Note 4)

0

TA

Free Air Operating Temperature

0

ns

ns

ns °C

70

Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V Note 3: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V Note 4: TA = 25°C and VCC = 5V.

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol

Parameter

Conditions

VI

Input Clamp Voltage

VCC = Min, II = −18 mA

VOH

HIGH Level

VCC = Min, IOH = Max

Output Voltage

VIL = Max, VIH = Min

VOL

II

2.7

Typ (Note 5)

Max

Units

−1.5

V

3.4

V

LOW Level

VCC = Min, IOL = Max

Output Voltage


0.35

0.5

IOL = 4 mA, VCC = Min

0.25

0.4

Input Current @ Max

0.4

VCC = Max, VI = 7V

Input Voltage IIH

Min

Shift/Load

0.3

Others

0.1

HIGH Level

VCC = Max

Shift/Load

60

Input Current

VI = 2.7V

Others

20

LOW Level

VCC = Max

Shift/Load

−1.2

Input Current

VI = 0.4V

Others

−0.4

IOS

Short Circuit Output Current

VCC = Max (Note 6)

ICC

Supply Current

VCC = Max (Note 7)

IIL

−20 21

V

mA µA mA

−100

mA

36

mA

Note 5: All typicals are at VCC = 5V, TA = 25° C. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 7: With all outputs OPEN, clock inhibit and shift/load at 4.5V, and a clock pulse applied to the CLOCK input, ICC is measured first with the parallel inputs at 4.5V, then again grounded.

3


DM74LS165

Absolute Maximum Ratings(Note 1)

DM74LS165

Switching Characteristics at VCC = 5V and TA = 25°C Symbol

Parameter

fMAX


tPLH

Propagation Delay Time LOW-to-HIGH Level Output

tPHL

Propagation Delay Time HIGH-to-LOW Level Output

tPLH


tPHL


tPLH


tPHL


tPLH


tPHL



CL = 15 pF

From (Input) To (Output)

Min

Max

25

RL = 2 kΩ, CL = 50 pF Min

Max

20

Units MHz

Load to Any Q

35

37

ns

Load to Any Q

35

42

ns

Clock to Any Q

40

42

ns

Clock to Any Q

40

47

ns

H to QH

25

27

ns

H to QH

30

37

ns

H to QH

30

32

ns

H to QH

25

32

ns

4

DM74LS165

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M16B

5


DM74LS165 8-Bit Parallel In/Serial Output Shift Registers

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com


6

Revised March 2000

DM74LS245 3-STATE Octal Bus Transceiver General Description

Features

These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control function implementation minimizes external timing requirements.

■ Bi-Directional bus transceiver in a high-density 20-pin package

The device allows data transmission from the A Bus to the B Bus or from the B Bus to the A Bus depending upon the logic level at the direction control (DIR) input. The enable input (G) can be used to disable the device so that the buses are effectively isolated.

■ Hysteresis at bus inputs improve noise margins

■ 3-STATE outputs drive bus lines directly ■ PNP inputs reduce DC loading on bus lines ■ Typical propagation delay times, port-to-port 8 ns ■ Typical enable/disable times 17 ns ■ IOL (sink current) 24 mA ■ IOH (source current) −15 mA


Package Number

Package Description

DM74LS245WM

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

DM74LS245SJ

M20D

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74LS245N

N20A



Connection Diagram

Function Table Enable

Direction

G

Control

Operation

DIR L

L

B Data to A Bus

L

H

A Data to B Bus

H

X

Isolation

H = HIGH Level L = LOW Level X = Irrelevant


DS006413


DM74LS245 3-STATE Octal Bus Transceiver

August 1986

DM74LS245

Absolute Maximum Ratings(Note 1) Supply Voltage

7V


Input Voltage 7V

DIR or G A or B

5.5V 0°C to +70°C


−65°C to +150°C


Recommended Operating Conditions Symbol

Parameter

Min

Nom

Max

4.75

5

5.25

Units

VCC

Supply Voltage

VIH


V

VIL


0.8

V

IOH


−15

mA

IOL


24

mA

TA


70

°C

2

V

0

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol

Parameter

Conditions

VI

Input Clamp Voltage


HYS

Hysteresis (VT+ − VT−)

VCC = Min

HIGH Level

VCC = Min, VIH = Min

VOH

Output Voltage

Min

0.2

2.4

VIL = Max, IOH = −3 mA VCC = Min, VIH = Min

Output Voltage

VIL = Max VIH = Min

IOZH IOZL

Off-State Output Current,

VCC = Max

HIGH Level Voltage Applied

VIL = Max

Off-State Output Current,

VIH = Min

LOW Level Voltage Applied II

Input Current at Maximum

VCC = Max

Input Voltage

V

0.4

V

3.4

V

2

VIL = 0.5V, IOH = Max VCC = Min

Units

2.7

VIL = Max, IOH = −1 mA

LOW Level

Max −1.5

VCC = Min, VIL = Min

VOL

Typ (Note 2)

IOL = 12 mA

0.4

IOL = Max

0.5

VO = 2.7V

20

µA

VO = 0.4V

−200

µA

A or B

VI = 5.5V

0.1

DIR or G

VI = 7V

0.1

V

mA

IIH

HIGH Level Input Current

VCC = Max, VI = 2.7V

20

µA

IIL

LOW Level Input Current


−0.2

mA

IOS


VCC = Max (Note 3)

−225

mA

ICC

Supply Current

Outputs HIGH

−40 VCC = Max

Outputs LOW Outputs at Hi-Z Note 2: All typicals are at VCC = 5V, TA = 25°C.

Note 3: Not more than one output should be shorted at a time, not to exceed one second duration


2

48

70

62

90

64

95

mA

VCC = 5V, TA = 25°C Symbol tPLH tPHL

Parameter

Conditions

Propagation Delay Time,

CL = 45 pF

LOW-to-HIGH Level Output

RL = 667Ω

Propagation Delay Time, HIGH-to-LOW Level Output

tPZL

Output Enable Time to LOW Level

tPZH

Output Enable Time to HIGH Level

tPLZ tPHZ

Output Disable Time

CL = 5 pF

from LOW Level

RL = 667Ω

Output Disable Time from HIGH Level

tPLH tPHL

Propagation Delay Time,

CL = 150 pF

LOW-to-HIGH Level Output

RL = 667Ω

Propagation Delay Time, HIGH-to-LOW Level Output

tPZL

Output Enable Time to LOW Level

tPZH

Output Enable Time to HIGH Level

3

Min

Max

Units

12

ns

12

ns

40

ns

40

ns

25

ns

25

ns

16

ns

17

ns

45

ns

45

ns


DM74LS245

Switching Characteristics

DM74LS245


20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B


4

DM74LS245


20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D

5


DM74LS245 3-STATE Octal Bus Transceiver


20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A




6

Revised March 2000

DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description

Features

These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

■ Choice of 8 latches or 8 D-type flip-flops in a single package ■ 3-STATE bus-driving outputs ■ Full parallel-access for loading ■ Buffered control inputs ■ P-N-P inputs reduce D-C loading on data lines

The eight latches of the DM74LS373 are transparent Dtype latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74LS374 are edge-triggered D-type flip flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.


Package Number

Package Description

DM74LS373WM

M20B


DM74LS373SJ

M20D


DM74LS373N

N20A


DM74LS374WM

M20B


DM74LS374SJ

M20D


IDM29901NC

N20A




DS006431


DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

April 1986

DM74LS373 • DM74LS374

Connection Diagrams DM74LS373

DM74LS374

Function Tables DM74LS373 Output

Enable

Control

G

L L

DM74LS374 D

Output

H

H

H

H

L

L

L

L

X

Q0

H

X

X

Z

H = HIGH Level (Steady State)

L = LOW Level (Steady State)

↑ = Transition from LOW-to-HIGH level

Output

Clock

D

Output

L

↑

H

H

L

↑

L

L

L

L

X

Q0

X

X

Z

Control

H X = Don’t Care

Z = High Impedance State

Q0 = The level of the output before steady-state input conditions were established.

Logic Diagrams DM74LS373 Transparent Latches


DM74LS374 Positive-Edge-Triggered Flip-Flops

2

Supply Voltage


7V

Input Voltage

7V −65°C to +150°C


0°C to +70°C


DM74LS373 Recommended Operating Conditions Symbol

Parameter

Min

Nom

Max

Units

4.75

5

5.25

V


0.8

V

VCC

Supply Voltage

VIH


VIL

2

V

IOH


−2.6

mA

IOL


24

mA

tW

Pulse Width

Enable HIGH

15

(Note 3)

Enable LOW

15

tSU

Data Setup Time (Note 2) (Note 3)

5↓

tH

Data Hold Time (Note 2) (Note 3)

20↓

TA


0

ns ns ns °C

70

Note 2: The symbol (↓) indicates the falling edge of the clock pulse is used for reference. Note 3: TA = 25°C and VCC = 5V.

DM74LS373 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol

Parameter

Conditions

VI

Input Clamp Voltage


VOH

HIGH Level


Output Voltage


VOL

LOW Level


Output Voltage


Min

2.4

Typ (Note 4)

Max

Units

−1.5

V

3.1

0.35

V

0.5


0.4

V

II

Input Current @ Max Input Voltage

VCC = Max, VI = 7V

0.1

IIH



20

µA

IIL



−0.4

mA

20

µA

−20

µA

−225

mA

40

mA

IOZH

Off-State Output Current with

VCC = Max, VO = 2.7V

HIGH Level Output Voltage Applied

VIH = Min, VIL = Max



LOW Level Output Voltage Applied


IOS


VCC = Max (Note 5)

ICC

Supply Current

VCC = Max, OC = 4.5V,

IOZL

−50

Dn, Enable = GND

24

mA

Note 4: All typicals are at VCC = 5V, TA = 25°C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.

3


DM74LS373 • DM74LS374

Absolute Maximum Ratings(Note 1)

DM74LS373 • DM74LS374

DM74LS373 Switching Characteristics at VCC = 5V and TA = 25°C RL = 667Ω Symbol

Parameter

CL = 45 pF

From (Input) To (Output)

tPLH

Propagation Delay Time

ns

Data to Q

18

27

ns

Enable to Q

30

38

ns

Enable to Q

30

36

ns

Output Control to Any Q

28

36

ns


36

50

ns


20

ns


25

ns

Propagation Delay Time Propagation Delay Time Propagation Delay Time HIGH-to-LOW Level Output

tPZH

Output Enable Time to HIGH Level Output

tPZL

Output Enable Time to LOW Level Output

tPHZ

Output Disable Time from HIGH Level Output (Note 6)

tPLZ

Output Disable Time from LOW Level Output (Note 6)

Units

Max 26

LOW-to-HIGH Level Output tPHL

CL = 150 pF Min

18

HIGH-to-LOW Level Output tPLH

Max

Data to Q


Min

Note 6: CL = 5 pF.

DM74LS374 Recommended Operating Conditions Symbol

Parameter

Min

Nom

Max

Units

4.75

5

5.25

V


0.8

V

VCC

Supply Voltage

VIH


VIL

2

V

IOH


−2.6

mA

IOL


24

mA

tW

Pulse Width

Clock HIGH

15

(Note 8)

Clock LOW

15

tSU

Data Setup Time (Note 7) (Note 8)

20↑

tH

Data Hold Time (Note 7) (Note 8)

1↑

TA


0

Note 7: The symbol (↑) indicates the rising edge of the clock pulse is used for reference. Note 8: TA = 25°C and V CC = 5V.


4

ns ns ns 70

°C

over recommended operating free air temperature range (unless otherwise noted) Symbol

Parameter

Conditions

VI

Input Clamp Voltage


VOH

HIGH Level


Output Voltage


VOL

LOW Level


Output Voltage


Min

2.4


Typ (Note 9)

Max

Units

−1.5

V

3.1

V

0.35

0.5

0.25

0.4

V

II

Input Current @ Max Input Voltage

VCC = Max, VI = 7V

0.1

IIH



20

µA

IIL



−0.4

mA

IOZH



HIGH Level Output Voltage Applied


20

µA

−20

µA

−225

mA

45

mA



LOW Level Output Voltage Applied


IOS


VCC = Max (Note 10)

ICC

Supply Current

VCC = Max, Dn = GND, OC = 4.5V

IOZL

−50 27

mA

Note 9: All typicals are at VCC = 5V, TA = 25°C. Note 10: Not more than one output should be shorted at a time, and the duration should not exceed one second.

DM74LS374 Switching Characteristics at VCC = 5V and TA = 25°C RL = 667Ω Symbol

CL = 45 pF

Parameter

Min fMAX


tPLH


35



tPZH

Output Enable Time to HIGH Level Output

tPZL

Output Enable Time to LOW Level Output

tPHZ

Output Disable Time from HIGH Level Output (Note 11)

tPLZ

Max

Output Disable Time from LOW Level Output (Note 11)

CL = 150 pF Min

Units

Max

20

MHz

28

32

ns

28

38

ns

28

44

ns

28

44

ns

20

ns

25

ns

Note 11: CL = 5 pF.

5


DM74LS373 • DM74LS374

DM74LS374 Electrical Characteristics

DM74LS373 • DM74LS374


20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B


6

DM74LS373 • DM74LS374


20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D

7


DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops


20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A




8

ADC0808/ADC0809 8-Bit µP Compatible A/D Converters with 8-Channel Multiplexer General Description

Features

The ADC0808, ADC0809 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can directly access any of 8-single-ended analog signals. The device eliminates the need for external zero and full-scale adjustments. Easy interfacing to microprocessors is provided by the latched and decoded multiplexer address inputs and latched TTL TRI-STATE ® outputs. The design of the ADC0808, ADC0809 has been optimized by incorporating the most desirable aspects of several A/D conversion techniques. The ADC0808, ADC0809 offers high speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device ideally suited to applications from process and machine control to consumer and automotive applications. For 16-channel multiplexer with common output (sample/hold port) see ADC0816 data sheet. (See AN-247 for more information.)

n Easy interface to all microprocessors n Operates ratiometrically or with 5 VDC or analog span adjusted voltage reference n No zero or full-scale adjust required n 8-channel multiplexer with address logic n 0V to 5V input range with single 5V power supply n Outputs meet TTL voltage level specifications n Standard hermetic or molded 28-pin DIP package n 28-pin molded chip carrier package n ADC0808 equivalent to MM74C949 n ADC0809 equivalent to MM74C949-1

Key Specifications n n n n n

Resolution Total Unadjusted Error Single Supply Low Power Conversion Time

8 Bits

± 1⁄2 LSB and ± 1 LSB 5 VDC 15 mW 100 µs

Block Diagram

DS005672-1

See Ordering Information

TRI-STATE ® is a registered trademark of National Semiconductor Corp.

© 1999 National Semiconductor Corporation

DS005672

www.national.com

ADC0808/ADC0809 8-Bit µP Compatible A/D Converters with 8-Channel Multiplexer

October 1999

ADC0808/ADC0809

Connection Diagrams

Molded Chip Carrier Package

Dual-In-Line Package

DS005672-12

Order Number ADC0808CCV or ADC0809CCV See NS Package V28A

DS005672-11

Order Number ADC0808CCN or ADC0809CCN See NS Package J28A or N28A

Ordering Information TEMPERATURE RANGE Error

± 1⁄2 LSB Unadjusted ± 1 LSB Unadjusted Package Outline

www.national.com

−40˚C to +85˚C ADC0808CCN

ADC0808CCV

ADC0809CCN

ADC0809CCV

N28A Molded DIP

V28A Molded Chip Carrier

2

−55˚C to +125˚C ADC0808CCJ

ADC0808CJ

J28A Ceramic DIP

J28A Ceramic DIP

Dual-In-Line Package (ceramic) Molded Chip Carrier Package Vapor Phase (60 seconds) Infrared (15 seconds) ESD Susceptibility (Note 8)

Supply Voltage (VCC) (Note 3) 6.5V Voltage at Any Pin −0.3V to (VCC+0.3V) Except Control Inputs Voltage at Control Inputs −0.3V to +15V (START, OE, CLOCK, ALE, ADD A, ADD B, ADD C) Storage Temperature Range −65˚C to +150˚C 875 mW Package Dissipation at TA = 25˚C Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (plastic) 260˚C

Operating Conditions

300˚C 215˚C 220˚C 400V (Notes 1, 2) TMIN≤TA≤TMAX −40˚C≤TA≤+85˚C −40˚C ≤ TA ≤ +85˚C 4.5 VDC to 6.0 VDC

Temperature Range (Note 1) ADC0808CCN,ADC0809CCN ADC0808CCV, ADC0809CCV Range of VCC (Note 1)

Electrical Characteristics Converter Specifications: VCC = 5 VDC = VREF+, VREF(−) = GND, TMIN≤TA≤TMAX and fCLK = 640 kHz unless otherwise stated. Symbol

Parameter

Conditions

Min

Typ

Max

Units

± 1⁄2 ± 3⁄4

LSB

±1 ± 11⁄4

LSB

VCC+0.10

VDC

ADC0808 Total Unadjusted Error

25˚C

(Note 5)

TMIN to TMAX

LSB

ADC0809

VREF(+)

Total Unadjusted Error

0˚C to 70˚C

(Note 5)

TMIN to TMAX

Input Resistance

From Ref(+) to Ref(−)

1.0

Analog Input Voltage Range

(Note 4) V(+) or V(−)

GND−0.10

Voltage, Top of Ladder

Measured at Ref(+)

Voltage, Center of Ladder

VREF(−)

Voltage, Bottom of Ladder

IIN

Comparator Input Current

VCC/2-0.1 Measured at Ref(−) fc = 640 kHz, (Note 6)

LSB

2.5

kΩ

VCC

VCC+0.1

V

VCC/2

VCC/2+0.1

V

2

µA

−0.1

0

−2

± 0.5

V

Electrical Characteristics Digital Levels and DC Specifications: ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75≤VCC≤5.25V, −40˚C≤TA≤+85˚C unless otherwise noted Symbol

Parameter

Conditions

Min

Typ

Max

Units

10

200

nA

1.0

µA

ANALOG MULTIPLEXER IOFF(+)

OFF Channel Leakage Current

VCC = 5V, VIN = 5V, TA = 25˚C

IOFF(−)

OFF Channel Leakage Current

TMIN to TMAX VCC = 5V, VIN = 0, TA = 25˚C

−200

TMIN to TMAX

−1.0

−10

nA µA

CONTROL INPUTS VIN(1)

Logical “1” Input Voltage

VIN(0)

Logical “0” Input Voltage

IIN(1)

Logical “1” Input Current

VCC−1.5

V

VIN = 15V

1.5

V

1.0

µA

(The Control Inputs) IIN(0)

Logical “0” Input Current

VIN = 0

−1.0

µA

(The Control Inputs) ICC

Supply Current

fCLK = 640 kHz

3

0.3

3.0

mA

www.national.com

ADC0808/ADC0809

Absolute Maximum Ratings (Notes 2, 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

ADC0808/ADC0809

Electrical Characteristics

(Continued)

Digital Levels and DC Specifications: ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75≤VCC≤5.25V, −40˚C≤TA≤+85˚C unless otherwise noted Symbol

Parameter

Conditions

Min

Typ

Max

Units

DATA OUTPUTS AND EOC (INTERRUPT) VOUT(1)

Logical “1” Output Voltage

VOUT(0)

Logical “0” Output Voltage

VOUT(0)

Logical “0” Output Voltage EOC

IOUT

TRI-STATE Output Current

VCC = 4.75V IOUT = −360µA IOUT = −10µA IO = 1.6 mA

2.4 4.5

V(min) V(min) 0.45

IO = 1.2 mA VO = 5V VO = 0

V

0.45

V

3

µA

−3

µA

Electrical Characteristics Timing Specifications VCC = VREF(+) = 5V, VREF(−) = GND, tr = tf = 20 ns and TA = 25˚C unless otherwise noted. Typ

Max

Units

tWS

Symbol

Minimum Start Pulse Width

Parameter (Figure 5)

Conditions

MIn

100

200

ns

tWALE

Minimum ALE Pulse Width

(Figure 5)

100

200

ns

ts

Minimum Address Set-Up Time

(Figure 5)

25

50

ns

tH

Minimum Address Hold Time

25

50

ns

tD

Analog MUX Delay Time

(Figure 5) RS = 0Ω (Figure 5)

1

2.5

µs

CL = 50 pF, RL = 10k (Figure 8) CL = 10 pF, RL = 10k (Figure 8) fc = 640 kHz, (Figure 5) (Note 7)

125

250

ns

125

250

ns

90

100

116

µs

10

640

1280

kHz

From ALE tH1, tH0

OE Control to Q Logic State

t1H, t0H

OE Control to Hi-Z

tc

Conversion Time

fc

Clock Frequency

tEOC

EOC Delay Time

(Figure 5)

0

8+2 µS

Clock Periods

CIN

Input Capacitance

At Control Inputs

10

15

pF

COUT

TRI-STATE Output

At TRI-STATE Outputs

10

15

pF

Capacitance Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to GND, unless othewise specified. Note 3: A zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC. Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCCn supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 100 mV, the output code will be correct. To achieve an absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage of 4.900 VDC over temperature variations, initial tolerance and loading. Note 5: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. See Figure 3. None of these A/Ds requires a zero or full-scale adjust. However, if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages can be adjusted to achieve this. See Figure 13. Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has little temperature dependence (Figure 6). See paragraph 4.0. Note 7: The outputs of the data register are updated one clock cycle before the rising edge of EOC. Note 8: Human body model, 100 pF discharged through a 1.5 kΩ resistor.

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Multiplexer. The device contains an 8-channel single-ended analog signal multiplexer. A particular input channel is selected by using the address decoder. Table 1 shows the input states for the address lines to select any channel. The address is latched into the decoder on the low-to-high transition of the address latch enable signal.

The successive approximation register (SAR) performs 8 iterations to approximate the input voltage. For any SAR type converter, n-iterations are required for an n-bit converter. Figure 2 shows a typical example of a 3-bit converter. In the ADC0808, ADC0809, the approximation technique is extended to 8 bits using the 256R network.

TABLE 1. SELECTED

ADDRESS LINE

ANALOG CHANNEL

C

B

A

IN0

L

L

L

IN1

L

L

H

IN2

L

H

L

IN3

L

H

H

IN4

H

L

L

IN5

H

L

H

IN6

H

H

L

IN7

H

H

H

The A/D converter’s successive approximation register (SAR) is reset on the positive edge of the start conversion (SC) pulse. The conversion is begun on the falling edge of the start conversion pulse. A conversion in process will be interrupted by receipt of a new start conversion pulse. Continuous conversion may be accomplished by tying the end-of-conversion (EOC) output to the SC input. If used in this mode, an external start conversion pulse should be applied after power up. End-of-conversion will go low between 0 and 8 clock pulses after the rising edge of start conversion. The most important section of the A/D converter is the comparator. It is this section which is responsible for the ultimate accuracy of the entire converter. It is also the comparator drift which has the greatest influence on the repeatability of the device. A chopper-stabilized comparator provides the most effective method of satisfying all the converter requirements.

CONVERTER CHARACTERISTICS The Converter The heart of this single chip data acquisition system is its 8-bit analog-to-digital converter. The converter is designed to give fast, accurate, and repeatable conversions over a wide range of temperatures. The converter is partitioned into 3 major sections: the 256R ladder network, the successive approximation register, and the comparator. The converter’s digital outputs are positive true. The 256R ladder network approach (Figure 1) was chosen over the conventional R/2R ladder because of its inherent monotonicity, which guarantees no missing digital codes. Monotonicity is particularly important in closed loop feedback control systems. A non-monotonic relationship can cause oscillations that will be catastrophic for the system. Additionally, the 256R network does not cause load variations on the reference voltage.

The chopper-stabilized comparator converts the DC input signal into an AC signal. This signal is then fed through a high gain AC amplifier and has the DC level restored. This technique limits the drift component of the amplifier since the drift is a DC component which is not passed by the AC amplifier. This makes the entire A/D converter extremely insensitive to temperature, long term drift and input offset errors.

Figure 4 shows a typical error curve for the ADC0808 as measured using the procedures outlined in AN-179.

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ADC0808/ADC0809

The bottom resistor and the top resistor of the ladder network in Figure 1 are not the same value as the remainder of the network. The difference in these resistors causes the output characteristic to be symmetrical with the zero and full-scale points of the transfer curve. The first output transition occurs when the analog signal has reached +1⁄2 LSB and succeeding output transitions occur every 1 LSB later up to full-scale.

Functional Description

ADC0808/ADC0809

Functional Description

(Continued)

DS005672-2

FIGURE 1. Resistor Ladder and Switch Tree

DS005672-13 DS005672-14

FIGURE 2. 3-Bit A/D Transfer Curve

FIGURE 3. 3-Bit A/D Absolute Accuracy Curve

DS005672-15

FIGURE 4. Typical Error Curve

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6

ADC0808/ADC0809

Timing Diagram

DS005672-4

FIGURE 5.

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ADC0808/ADC0809

Typical Performance Characteristics

DS005672-16

FIGURE 6. Comparator IIN vs VIN (VCC = VREF = 5V)

DS005672-17

FIGURE 7. Multiplexer RON vs VIN (VCC = VREF = 5V)

TRI-STATE Test Circuits and Timing Diagrams t1H, CL = 10 pF

t1H, tH1

DS005672-18

tH1, CL = 50 pF

DS005672-19

t0H, CL = 10 pF

t0H, tH0

DS005672-22

DS005672-21

DS005672-20

tH0, CL = 50 pF

DS005672-23

FIGURE 8. DX = Data point being measured DMAX = Maximum data limit DMIN = Minimum data limit A good example of a ratiometric transducer is a potentiometer used as a position sensor. The position of the wiper is directly proportional to the output voltage which is a ratio of the full-scale voltage across it. Since the data is represented as a proportion of full-scale, reference requirements are greatly reduced, eliminating a large source of error and cost for many applications. A major advantage of the ADC0808, ADC0809 is that the input voltage range is equal to the supply range so the transducers can be connected directly across the supply and their outputs connected directly into the multiplexer inputs, (Figure 9). Ratiometric transducers such as potentiometers, strain gauges, thermistor bridges, pressure transducers, etc., are suitable for measuring proportional relationships; however, many types of measurements must be referred to an absolute standard such as voltage or current. This means a sys-

Applications Information OPERATION 1.0 RATIOMETRIC CONVERSION The ADC0808, ADC0809 is designed as a complete Data Acquisition System (DAS) for ratiometric conversion systems. In ratiometric systems, the physical variable being measured is expressed as a percentage of full-scale which is not necessarily related to an absolute standard. The voltage input to the ADC0808 is expressed by the equation

(1) VIN = Input voltage into the ADC0808 Vfs = Full-scale voltage VZ = Zero voltage www.national.com

8

The top of the ladder, Ref(+), should not be more positive than the supply, and the bottom of the ladder, Ref(−), should not be more negative than ground. The center of the ladder voltage must also be near the center of the supply because the analog switch tree changes from N-channel switches to P-channel switches. These limitations are automatically satisfied in ratiometric systems and can be easily met in ground referenced systems.

(Continued)

tem reference must be used which relates the full-scale voltage to the standard volt. For example, if VCC = VREF = 5.12V, then the full-scale range is divided into 256 standard steps. The smallest standard step is 1 LSB which is then 20 mV. 2.0 RESISTOR LADDER LIMITATIONS The voltages from the resistor ladder are compared to the selected into 8 times in a conversion. These voltages are coupled to the comparator via an analog switch tree which is referenced to the supply. The voltages at the top, center and bottom of the ladder must be controlled to maintain proper operation.

Figure 10 shows a ground referenced system with a separate supply and reference. In this system, the supply must be trimmed to match the reference voltage. For instance, if a 5.12V is used, the supply should be adjusted to the same voltage within 0.1V.

DS005672-7

FIGURE 9. Ratiometric Conversion System The top and bottom ladder voltages cannot exceed VCC and ground, respectively, but they can be symmetrically less than VCC and greater than ground. The center of the ladder voltage should always be near the center of the supply. The sensitivity of the converter can be increased, (i.e., size of the LSB steps decreased) by using a symmetrical reference system. In Figure 13, a 2.5V reference is symmetrically centered about VCC/2 since the same current flows in identical resistors. This system with a 2.5V reference allows the LSB bit to be half the size of a 5V reference system.

The ADC0808 needs less than a milliamp of supply current so developing the supply from the reference is readily accomplished. In Figure 11 a ground referenced system is shown which generates the supply from the reference. The buffer shown can be an op amp of sufficient drive to supply the milliamp of supply current and the desired bus drive, or if a capacitive bus is driven by the outputs a large capacitor will supply the transient supply current as seen in Figure 12. The LM301 is overcompensated to insure stability when loaded by the 10 µF output capacitor.

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ADC0808/ADC0809

Applications Information

ADC0808/ADC0809


(Continued)

DS005672-24

FIGURE 10. Ground Referenced Conversion System Using Trimmed Supply

DS005672-25

FIGURE 11. Ground Referenced Conversion System with Reference Generating VCC Supply

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10

ADC0808/ADC0809


(Continued)

DS005672-26

FIGURE 12. Typical Reference and Supply Circuit

DS005672-27

RA = RB *Ratiometric transducers

FIGURE 13. Symmetrically Centered Reference The output code N for an arbitrary input are the integers within the range:

3.0 CONVERTER EQUATIONS The transition between adjacent codes N and N+1 is given by:

(4) Where: VIN = Voltage at comparator input VREF(+) = Voltage at Ref(+) VREF(−) = Voltage at Ref(−) VTUE = Total unadjusted error voltage (typically VREF(+)÷512)

(2) The center of an output code N is given by:

(3)

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ADC0808/ADC0809


If no filter capacitors are used at the analog inputs and the signal source impedances are low, the comparator input current should not introduce converter errors, as the transient created by the capacitance discharge will die out before the comparator output is strobed. If input filter capacitors are desired for noise reduction and signal conditioning they will tend to average out the dynamic comparator input current. It will then take on the characteristics of a DC bias current whose effect can be predicted conventionally.

(Continued)

4.0 ANALOG COMPARATOR INPUTS The dynamic comparator input current is caused by the periodic switching of on-chip stray capacitances. These are connected alternately to the output of the resistor ladder/ switch tree network and to the comparator input as part of the operation of the chopper stabilized comparator. The average value of the comparator input current varies directly with clock frequency and with VIN as shown in Figure 6.

Typical Application

DS005672-10

*Address latches needed for 8085 and SC/MP interfacing the ADC0808 to a microprocessor

TABLE 2. Microprocessor Interface Table PROCESSOR

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READ

WRITE

INTERRUPT (COMMENT)

8080

MEMR

MEMW

INTR (Thru RST Circuit)

8085

RD

WR

INTR (Thru RST Circuit)

Z-80

RD

WR

INT (Thru RST Circuit, Mode 0)

SC/MP

NRDS

NWDS

SA (Thru Sense A)

6800

VMA • φ2 • R/W

VMA • φ • R/W

IRQA or IRQB (Thru PIA)

12

ADC0808/ADC0809

Physical Dimensions

inches (millimeters) unless otherwise noted

Molded Dual-In-Line Package (N) Order Number ADC0808CCN or ADC0809CCN NS Package Number N28B

Molded Chip Carrier (V) Order Number ADC0808CCV or ADC0809CCV NS Package Number V28A 13

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ADC0808/ADC0809 8-Bit µP Compatible A/D Converters with 8-Channel Multiplexer

Notes

LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

DAC0808 8-Bit D/A Converter General Description

Features

The DAC0808 is an 8-bit monolithic digital-to-analog converter (DAC) featuring a full scale output current settling time of 150 ns while dissipating only 33 mW with ± 5V supplies. No reference current (IREF) trimming is required for most applications since the full scale output current is typically ± 1 LSB of 255 IREF/256. Relative accuracies of better than ± 0.19% assure 8-bit monotonicity and linearity while zero level output current of less than 4 µA provides 8-bit zero accuracy for IREF≥2 mA. The power supply currents of the DAC0808 is independent of bit codes, and exhibits essentially constant device characteristics over the entire supply voltage range. The DAC0808 will interface directly with popular TTL, DTL or CMOS logic levels, and is a direct replacement for the MC1508/MC1408. For higher speed applications, see DAC0800 data sheet.

n n n n

Relative accuracy: ± 0.19% error maximum Full scale current match: ± 1 LSB typ Fast settling time: 150 ns typ Noninverting digital inputs are TTL and CMOS compatible n High speed multiplying input slew rate: 8 mA/µs n Power supply voltage range: ± 4.5V to ± 18V n Low power consumption: 33 mW @ ± 5V

Block and Connection Diagrams

DS005687-1

Dual-In-Line Package

DS005687-2

Top View Order Number DAC0808 See NS Package M16A or N16A

© 2001 National Semiconductor Corporation

DS005687

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DAC0808 8-Bit D/A Converter

May 1999

DAC0808

Block and Connection Diagrams

(Continued)

Small-Outline Package

DS005687-13

Ordering Information ACCURACY

OPERATING TEMPERATURE RANGE

8-bit

0˚C≤TA≤+75˚C

N PACKAGE (N16A) (Note 1) DAC0808LCN

Note 1: Devices may be ordered by using either order number.

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2

MC1408P8

SO PACKAGE (M16A) DAC0808LCM

Storage Temperature Range Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (Plastic) Dual-In-Line Package (Ceramic) Surface Mount Package Vapor Phase (60 seconds) Infrared (15 seconds)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage VCC VEE Digital Input Voltage, V5–V12 Applied Output Voltage, VO Reference Current, I14 Reference Amplifier Inputs, V14, V15 Power Dissipation (Note 4) ESD Susceptibility (Note 5)

−10 VDC −11 VDC

+18 VDC −18 VDC to +18 VDC to +18 VDC 5 mA VCC, VEE 1000 mW TBD

−65˚C to +150˚C 260˚C 300˚C 215˚C 220˚C

Operating Ratings TMIN ≤ TA ≤ TMAX 0 ≤TA ≤ +75˚C

Temperature Range DAC0808

Electrical Characteristics (VCC = 5V, VEE = −15 VDC, VREF/R14 = 2 mA, and all digital inputs at high logic level unless otherwise noted.) Symbol Er

Parameter Relative Accuracy (Error Relative

Conditions

Min

Typ

Max

Units

(Figure 4)

%

to Full Scale IO)

± 0.19

DAC0808LC (LM1408-8) Settling Time to Within ⁄ LSB

TA =25˚C (Note 7),

(Includes tPLH)

(Figure 5) TA = 25˚C, (Figure 5)

12

tPLH, tPHL


TCIO

Output Full Scale Current Drift

MSB

Digital Input Logic Levels

VIH

High Level, Logic “1”

VIL

Low Level, Logic “0”

MSB

I15

IO

Digital Input Current

%

150 30

ns 100

ns

± 20

ppm/˚C

(Figure 3) 2

VDC 0.8

VDC

(Figure 3)

High Level

VIH = 5V

0

0.040

mA

Low Level

VIL = 0.8V

−0.003

−0.8

mA

Reference Input Bias Current

(Figure 3)

−1

−3

µA

Output Current Range

(Figure 3)

Output Current

VEE = −5V

0

2.0

2.1

mA

VEE = −15V, TA = 25˚C

0

2.0

4.2

mA

1.9

1.99

2.1

mA

0

4

µA

VREF = 2.000V, R14 = 1000Ω, (Figure 3)

SRIREF

Output Current, All Bits Low

(Figure 3)

Output Voltage Compliance (Note 3)

Er ≤ 0.19%, TA = 25˚C

VEE =−5V, IREF =1 mA

−0.55, +0.4

VDC

VEE Below −10V

−5.0, +0.4

VDC

Reference Current Slew Rate

(Figure 6)

Output Current Power Supply

−5V ≤ VEE ≤ −16.5V

4

8

mA/µs

0.05

2.7

µA/V

2.3

22

mA

−4.3

−13

mA

Sensitivity Power Supply Current (All Bits

(Figure 3)

Low) ICC IEE Power Supply Voltage Range

TA = 25˚C, (Figure 3)

VCC

4.5

5.0

5.5

VDC

VEE

−4.5

−15

−16.5

VDC

Power Dissipation

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DAC0808

Absolute Maximum Ratings (Note 2)

DAC0808

Electrical Characteristics

(Continued)

(VCC = 5V, VEE = −15 VDC, VREF/R14 = 2 mA, and all digital inputs at high logic level unless otherwise noted.) Symbol

Parameter All Bits Low All Bits High

Typ

Max

Units

VCC = 5V, VEE = −5V

Conditions

Min

33

170

mW


106

305

mW


90

mW

VCC = 15V, VEE = −15V

160

mW

Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 3: Range control is not required. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maixmum Ratings, whichever is lower. For this device, TJMAX = 125˚C, and the typical junction-to-ambient thermal resistance of the dual-in-line J package when the board mounted is 100˚C/W. For the dual-in-line N package, this number increases to 175˚C/W and for the small outline M package this number is 100˚C/W. Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Note 6: All current switches are tested to guarantee at least 50% of rated current. Note 7: All bits switched. Note 8: Pin-out numbers for the DAL080X represent the dual-in-line package. The small outline package pinout differs from the dual-in-line package.

Typical Application

DS005687-23

DS005687-3

FIGURE 1. +10V Output Digital to Analog Converter (Note 8)

Typical Performance Characteristics Logic Input Current vs Input Voltage

VCC = 5V, VEE = −15V, TA = 25˚C, unless otherwise noted Logic Threshold Voltage vs Temperature

Bit Transfer Characteristics

DS005687-14

DS005687-15 DS005687-16

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DAC0808


VCC = 5V, VEE = −15V, TA = 25˚C, unless otherwise

noted (Continued) Output Current vs Output Voltage (Output Voltage Compliance)

Output Voltage Compliance vs Temperature

Typical Power Supply Current vs Temperature

DS005687-18 DS005687-19

DS005687-17

Typical Power Supply Current vs VEE

Typical Power Supply Current vs VCC

DS005687-20

Reference Input Frequency Response

DS005687-21

DS005687-22

Unless otherwise specified: R14 = R15 = 1 kΩ, C = 15 pF, pin 16 to VEE; RL = 50Ω, pin 4 to ground. Curve A: Large Signal Bandwidth Method of Figure 7, VREF = 2 Vp-p offset 1V above ground. Curve B: Small Signal Bandwidth Method of Figure 7, RL = 250Ω, VREF = 50 mVp-p offset 200 mV above ground. Curve C: Large and Small Signal Bandwidth Method of Figure 9 (no op amp, RL = 50Ω), RS = 50Ω, VREF = 2V, VS = 100 mVp-p centered at 0V.

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FIGURE 2. Equivalent Circuit of the DAC0808 Series (Note 8)

DS005687-4

DAC0808

DAC0808

Test Circuits

DS005687-6

VI and I1 apply to inputs A1–A8. The resistor tied to pin 15 is to temperature compensate the bias current and may not be necessary for all applications.

and AN = “1” if AN is at high level AN = “0” if AN is at low level

FIGURE 3. Notation Definitions Test Circuit (Note 8)

DS005687-7

FIGURE 4. Relative Accuracy Test Circuit (Note 8)

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DAC0808

Test Circuits

(Continued)

DS005687-8

FIGURE 5. Transient Response and Settling Time (Note 8)

DS005687-9

FIGURE 6. Reference Current Slew Rate Measurement (Note 8)

DS005687-10

FIGURE 7. Positive VREF (Note 8)

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DAC0808

Test Circuits

(Continued)

DS005687-11

FIGURE 8. Negative VREF (Note 8)

DS005687-12

FIGURE 9. Programmable Gain Amplifier or Digital Attenuator Circuit (Note 8) For bipolar reference signals, as in the multiplying mode, R15 can be tied to a negative voltage corresponding to the minimum input level. It is possible to eliminate R15 with only a small sacrifice in accuracy and temperature drift. The compensation capacitor value must be increased with increases in R14 to maintain proper phase margin; for R14 values of 1, 2.5 and 5 kΩ, minimum capacitor values are 15, 37 and 75 pF. The capacitor may be tied to either VEE or ground, but using VEE increases negative supply rejection. A negative reference voltage may be used if R14 is grounded and the reference voltage is applied to R15 as shown in Figure 8. A high input impedance is the main

Application Hints REFERENCE AMPLIFIER DRIVE AND COMPENSATION The reference amplifier provides a voltage at pin 14 for converting the reference voltage to a current, and a turn-around circuit or current mirror for feeding the ladder. The reference amplifier input currrent, I14, must always flow into pin 14, regardless of the set-up method or reference voltage polarity. Connections for a positive voltage are shown in Figure 7. The reference voltage source supplies the full current I14. 9

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DAC0808

Application Hints

der. The reference current may drift with temperature, causing a change in the absolute accuracy of output current. However, the DAC0808 has a very low full-scale current drift with temperature.

(Continued)

advantage of this method. Compensation involves a capacitor to VEE on pin 16, using the values of the previous paragraph. The negative reference voltage must be at least 4V above the VEE supply. Bipolar input signals may be handled by connecting R14 to a positive reference voltage equal to the peak positive input level at pin 15. When a DC reference voltage is used, capacitive bypass to ground is recommended. The 5V logic supply is not recommended as a reference voltage. If a well regulated 5V supply which drives logic is to be used as the reference, R14 should be decoupled by connecting it to 5V through another resistor and bypassing the junction of the 2 resistors with 0.1 µF to ground. For reference voltages greater than 5V, a clamp diode is recommended between pin 14 and ground. If pin 14 is driven by a high impedance such as a transistor current source, none of the above compensation methods apply and the amplifier must be heavily compensated, decreasing the overall bandwidth.

The DAC0808 series is guaranteed accurate to within ± 1⁄2 LSB at a full-scale output current of 1.992 mA. This corresponds to a reference amplifier output current drive to the ladder network of 2 mA, with the loss of 1 LSB (8 µA) which is the ladder remainder shunted to ground. The input current to pin 14 has a guaranteed value of between 1.9 and 2.1 mA, allowing some mismatch in the NPN current source pair. The accuracy test circuit is shown in Figure 4. The 12-bit converter is calibrated for a full-scale output current of 1.992 mA. This is an optional step since the DAC0808 accuracy is essentially the same between 1.5 and 2.5 mA. Then the DAC0808 circuits’ full-scale current is trimmed to the same value with R14 so that a zero value appears at the error amplifier output. The counter is activated and the error band may be displayed on an oscilloscope, detected by comparators, or stored in a peak detector. Two 8-bit D-to-A converters may not be used to construct a 16-bit accuracy D-to-A converter. 16-bit accuracy implies a total error of ± 1⁄2 of one part in 65,536 or ± 0.00076%, which is much more accurate than the ± 0.019% specification provided by the DAC0808.

OUTPUT VOLTAGE RANGE The voltage on pin 4 is restricted to a range of −0.55 to 0.4V when VEE = −5V due to the current switching methods employed in the DAC0808. The negative output voltage compliance of the DAC0808 is extended to −5V where the negative supply voltage is more negative than −10V. Using a full-scale current of 1.992 mA and load resistor of 2.5 kΩ between pin 4 and ground will yield a voltage output of 256 levels between 0 and −4.980V. Floating pin 1 does not affect the converter speed or power dissipation. However, the value of the load resistor determines the switching time due to increased voltage swing. Values of RL up to 500Ω do not significantly affect performance, but a 2.5 kΩ load increases worst-case settling time to 1.2 µs (when all bits are switched ON). Refer to the subsequent text section on Settling Time for more details on output loading.

MULTIPLYING ACCURACY The DAC0808 may be used in the multiplying mode with 8-bit accuracy when the reference current is varied over a range of 256:1. If the reference current in the multiplying mode ranges from 16 µA to 4 mA, the additional error contributions are less than 1.6 µA. This is well within 8-bit accuracy when referred to full-scale. A monotonic converter is one which supplies an increase in current for each increment in the binary word. Typically, the DAC0808 is monotonic for all values of reference current above 0.5 mA. The recommended range for operation with a DC reference current is 0.5 to 4 mA.

OUTPUT CURRENT RANGE The output current maximum rating of 4.2 mA may be used only for negative supply voltages more negative than −8V, due to the increased voltage drop across the resistors in the reference current amplifier.

SETTLING TIME The worst-case switching condition occurs when all bits are switched ON, which corresponds to a low-to-high transition for all bits. This time is typically 150 ns for settling to within ± 1⁄2 LSB, for 8-bit accuracy, and 100 ns to 1⁄2 LSB for 7 and 6-bit accuracy. The turn OFF is typically under 100 ns. These times apply when RL ≤ 500Ω and CO ≤ 25 pF. Extra care must be taken in board layout since this is usually the dominant factor in satisfactory test results when measuring settling time. Short leads, 100 µF supply bypassing for low frequencies, and minimum scope lead length are all mandatory.

ACCURACY Absolute accuracy is the measure of each output current level with respect to its intended value, and is dependent upon relative accuracy and full-scale current drift. Relative accuracy is the measure of each output current level as a fraction of the full-scale current. The relative accuracy of the DAC0808 is essentially constant with temperature due to the excellent temperature tracking of the monolithic resistor lad-

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DAC0808

Physical Dimensions

inches (millimeters) unless otherwise noted

Small Outline Package Order Number DAC0808LCM NS Package Number M16A

Dual-In-Line Package Order Number DAC0808 NS Package Number N16A

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DAC0808 8-Bit D/A Converter

Notes

LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: [email protected]

www.national.com

National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected]

National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

This datasheet has been downloaded from: www.DatasheetCatalog.com Datasheets for electronic components.


LM741

Single Operational Amplifier Features

Description

• • • • •

The LM741 series are general purpose operational amplifiers. It is intended for a wide range of analog applications. The high gain and wide range of operating voltage provide superior performance in intergrator, summing amplifier, and general feedback applications.

Short circuit protection Excellent temperature stability Internal frequency compensation High Input voltage range Null of offset

8-DIP

1

8-SOP

1

Internal Block Diagram

Rev. 1.0.1 ©2001 Fairchild Semiconductor Corporation

LM741

Schematic Diagram

Absolute Maximum Ratings (TA = 25°C) Parameter Supply Voltage Differential Input Voltage Input Voltage Output Short Circuit Duration Power Dissipation

2

Symbol

Value

Unit

VCC

±18

V

VI(DIFF)

30

V

VI

±15

V

-

Indefinite

-

PD

500

mW

Operating Temperature Range LM741C LM741I

TOPR

0 ~ + 70 -40 ~ +85

°C


TSTG

-65 ~ + 150

°C

LM741

Electrical Characteristics (VCC = 15V, VEE = - 15V. TA = 25 °C, unless otherwise specified) Parameter

Symbol

Conditions

LM741C/LM741I

Unit

Min.

Typ.

Max.

RS≤10KΩ

-

2.0

6.0

RS≤50Ω

-

-

-

VCC = ±20V

-

±15

-

mV

Input Offset Voltage

VIO

Input Offset Voltage Adjustment Range

VIO(R)

Input Offset Current

IIO

-

-

20

200

nA

IBIAS

-

-

80

500

nA

0.3

2.0

-

MΩ

-

±12

±13

-

V

VCC =±20V, VO(P-P) =±15V

-

-

-

VCC =±15V, VO(P-P) =±10V

20

200

-

-

-

25

-

RL≥10KΩ

-

-

-

RL≥2KΩ

-

-

-

RL≥10KΩ

±12

±14

-

RL≥2KΩ

±10

±13

-

RS≤10KΩ, VCM = ±12V

70

90

-

RS≤50Ω, VCM = ±12V

-

-

-

VCC = ±15V to VCC = ±15V RS≤50Ω

-

-

-

VCC = ±15V to VCC = ±15V RS≤10KΩ

77

96

-

-

0.3

-

µs

-

10

-

%

-

-

-

MHz

-

0.5

-

V/µs mA

Input Bias Current Input Resistance (Note1) Input Voltage Range

RI

VCC =±20V

VI(R) RL≥2KΩ

Large Signal Voltage Gain

Output Short Circuit Current

GV

ISC VCC = ±20V

Output Voltage Swing

Common Mode Rejection Ratio

Power Supply Rejection Ratio

VO(P-P)

CMRR

PSRR

Transient

Rise Time

TR

Response

Overshoot

OS

VCC = ±15V

Unity Gain

V/mV

BW

Slew Rate

SR

Unity Gain

Supply Current

ICC

RL= ∞Ω

-

1.5

2.8

VCC = ±20V

-

-

-

VCC = ±15V

-

50

85

PC

mA

V

dB

dB

Bandwidth

Power Consumption

-

mV

mW

Note: 1. Guaranteed by design.

3

LM741

Electrical Characteristics ( 0°C ≤TA≤70 °C VCC = ±15V, unless otherwise specified) The following specification apply over the range of 0°C ≤ TA ≤ +70 °C for the LM741C; and the -40°C ≤ TA ≤ +85 °C for the LM741I Parameter Input Offset Voltage Input Offset Voltage Drift Input Offset Current Input Offset Current Drift Input Bias Current Input Resistance (Note1) Input Voltage Range

Symbol VIO

Conditions

Min.

Typ.

Max.

RS≤50Ω

-

-

-

RS≤10KΩ

-

-

7.5

-

-

-

-

-

∆IIO/∆T

-

-

-

IBIAS

-

-

-

0.8

µA

-

-

-

MΩ V

RI

VCC = ±20V

VO(P-P)

Power Supply Rejection Ratio

PSRR

4

GV

±13

-

-

-

-

RS≥2KΩ

-

-

-

RS≥10KΩ

±12

±14

-

RS≥2KΩ

±10

±13

-

10

-

40

70

90

-

-

-

-

-

-

-

77

96

-

VCC = ±20V, VO(P-P) = ±15V

-

-

-

VCC = ±15V, VO(P.P) = ±10V

15

-

-

VCC = ±15V, VO(P-P) = ±2V

-

-

-

RS≤10KΩ, VCM = ±12V RS≤50Ω, VCM = ±12V VCC = ±20V to ±5V

RS≥2KΩ

RS≤50Ω RS≤10KΩ

nA nA/ °C

±12

-

ISC

300

RS≥10KΩ

-

VI(R)

CMRR

Note : 1. Guaranteed by design.

µV/ °C

-

Common Mode Rejection Ratio

Large Signal Voltage Gain

mV

IIO

VCC =±15V Output Short Circuit Current

Unit

∆VIO/∆T

VCC =±20V Output Voltage Swing

LM741C/LM741I

V

mA dB dB

V/mV

LM741


Figure 1. Output Resistance vs Frequency

Figure 2. Input Resistance and Input Capacitance vs Frequency

Figure 3. Input Bias Current vs Ambient Temperature

Figure 4. Power Consumption vs Ambient Temperature

Figure 5. Input Offset Current vs Ambient Temperature

Figure 6. Input Resistance vs Ambient Temperature

5

LM741

Typical Performance Characteristics (continued)

6

Figure 7. Normalized DC Parameters vs Ambient Temperature

Figure 8. Frequency Characteristics vs Ambient Temperature

Figure 9. Frequency Characteristics vs Supply Voltage

Figure 10. Output Short Circuit Current vs Ambient Temperature

Figure 11. Transient Response

Figure 12. Common-Mode Rejection Ratio vs Frequency

LM741

Typical Performance Characteristics (continued)

Figure 13. Voltage Follower Large Signal Pulse Response

Figure 14. Output Swing and Input Range vs Supply Voltage

7

LM741

Mechanical Dimensions Package

2.54 0.100 5.08 MAX 0.200 7.62 0.300

3.40 ±0.20 0.134 ±0.008

+0.10

0.25 –0.05 +0.004

0~15°

8

0.010 –0.002

3.30 ±0.30 0.130 ±0.012 0.33 0.013 MIN

0.060 ±0.004

#5

1.524 ±0.10

#4

0.018 ±0.004

#8 9.60 MAX 0.378

#1

9.20 ±0.20 0.362 ±0.008

(

6.40 ±0.20 0.252 ±0.008

0.46 ±0.10

0.79 ) 0.031

8-DIP

LM741

Mechanical Dimensions (Continued) Package

8-SOP MIN

#5

6.00 ±0.30 0.236 ±0.012

8° 0~

+0.10 0.15 -0.05 +0.004 0.006 -0.002

MAX0.10 MAX0.004

1.80 MAX 0.071

3.95 ±0.20 0.156 ±0.008

5.72 0.225

0.41 ±0.10 0.016 ±0.004

#4

1.27 0.050

#8 5.13 MAX 0.202

#1

4.92 ±0.20 0.194 ±0.008

(

0.56 ) 0.022

1.55 ±0.20 0.061 ±0.008

0.1~0.25 0.004~0.001

0.50 ±0.20 0.020 ±0.008

9

LM741

Ordering Information Product Number

Package

LM741CN

8-DIP

LM741CM

8-SOP

LM741IN

8-DIP

Operating Temperature 0 ~ + 70°C -40 ~ + 85°C

DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com 6/1/01 0.0m 001 Stock#DSxxxxxxxx  2001 Fairchild Semiconductor Corporation

Philips Semiconductors Linear Products

Product specification

Timer

NE/SA/SE555/SE555C

DESCRIPTION

PIN CONFIGURATIONS

The 555 monolithic timing circuit is a highly stable controller capable of producing accurate time delays, or oscillation. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For a stable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200mA.

D, N, FE Packages GND 1

8

VCC

TRIGGER 2

7

DISCHARGE

OUTPUT 3

6

THRESHOLD

RESET 4

5

CONTROL VOLTAGE

FEATURES

F Package

• Turn-off time less than 2µs • Max. operating frequency greater than 500kHz • Timing from microseconds to hours • Operates in both astable and monostable modes • High output current • Adjustable duty cycle • TTL compatible • Temperature stability of 0.005% per °C

GND 1

14

VCC

NC 2

13

NC

TRIGGER 3

12

DISCHARGE

OUTPUT 4

11

NC

NC 5

10

THRESHOLD

RESET 6

9

NC

NC 7

8

CONTROL VOLTAGE

TOP VIEW

APPLICATIONS

• Precision timing • Pulse generation • Sequential timing • Time delay generation • Pulse width modulation ORDERING INFORMATION TEMPERATURE RANGE

ORDER CODE

DWG #

8-Pin Plastic Small Outline (SO) Package

DESCRIPTION

0 to +70°C

NE555D

0174C

8-Pin Plastic Dual In-Line Package (DIP)

0 to +70°C

NE555N

0404B


-40°C to +85°C

SA555N

0404B

8-Pin Plastic Small Outline (SO) Package

-40°C to +85°C

SA555D

0174C

8-Pin Hermetic Ceramic Dual In-Line Package (CERDIP)

-55°C to +125°C

SE555CFE


-55°C to +125°C

SE555CN

0404B


-55°C to +125°C

SE555N

0405B

8-Pin Hermetic Cerdip

-55°C to +125°C

SE555FE

14-Pin Ceramic Dual In-Line Package (CERDIP)

0 to +70°C

NE555F

0581B


-55°C to +125°C

SE555F

0581B


-55°C to +125°C

SE555CF

0581B

August 31, 1994

346

853-0036 13721



Timer

NE/SA/SE555/SE555C

BLOCK DIAGRAM VCC 8

R THRESHOLD 6

CONTROL VOLTAGE 5

COMPARATOR

R TRIGGER 2

COMPARATOR R

DISCHARGE 7

RESET FLIP FLOP

4

OUTPUT STAGE

3

1

OUTPUT

GND

EQUIVALENT SCHEMATIC FM CONTROL VOLTAGE VCC

R1 4.7K

R2 330

R3 4.7 K

R 4 1 K

R 7 5 K

R12 6.8K

Q21 Q6

Q5

Q7

Q9 Q22 Q8

Q1 THRESHOLD

Q19

R1 0 82. K

Q4 Q2

R13 3.9K

Q3

OUTPUT Q23 C

R5 10 K

R8 5K

Q11 Q12 Q10

CB Q18 E

Q16 Q25 R9 5K

R6 100K

DISCHARGE Q14 R16 100

Pin numbers are for 8-Pin package

August 31, 1994

R14 220 Q24

Q15

RESET

NOTE:

Q20 Q17

Q13

TRIGGER

GND

R11 4.7K

B

347

R15 4.7K



Timer

NE/SA/SE555/SE555C

ABSOLUTE MAXIMUM RATINGS SYMBOL

PARAMETER

RATING

UNIT

SE555

+18

V

NE555, SE555C, SA555

+16

V

600

mW

NE555

0 to +70

°C

SA555

-40 to +85

°C

SE555, SE555C

-55 to +125

°C

-65 to +150

°C

+300

°C

Supply voltage VCC PD

Maximum allowable power dissipation1

TA

Operating ambient temperature range

TSTG

Storage temperature range

TSOLD

Lead soldering temperature (10sec max)

NOTES: 1. The junction temperature must be kept below 125°C for the D package and below 150°C for the FE, N and F packages. At ambient temperatures above 25°C, where this limit would be derated by the following factors: D package 160°C/W FE package 150°C/W N package 100°C/W F package 105°C/W

August 31, 1994

348



Timer

NE/SA/SE555/SE555C

DC AND AC ELECTRICAL CHARACTERISTICS TA = 25°C, VCC = +5V to +15 unless otherwise specified. SYMBOL

PARAMETER

VCC

Supply voltage

ICC

Supply current (low state)1 Timing error (monostable)

tM

Initial accuracy2

∆tM/∆T

Drift with temperature

∆tM/∆VS

TEST CONDITIONS

4.5

V mA

VCC=15V, RL=∞

10

12

10

15

mA

0.5

2.0

1.0

3.0

%

30

100

50

150

ppm/°C

0.05

0.2

0.1

0.5

%/V

6

5

RA=2kΩ to 100kΩ C=0.1µF

RA, RB=1kΩ to 100kΩ C=0.1µF

4

500

Drift with supply voltage

Threshold current3

VTRIG

Trigger voltage

UNIT

6

VCC=15V

ITH

4.5

Max 16

Drift with temperature

Threshold voltage

18

Typ 3

∆tA/∆T

VTH

Min

5

Initial accuracy2

Control voltage level

NE555/SE555C Max

3

tA

VC

Typ

VCC=5V, RL=∞

Drift with supply voltage Timing error (astable)

∆tA/∆VS

SE555 Min

13

%

500

ppm/°C

0.15

0.6

0.3

1

%/V

VCC=15V

9.6

10.0

10.4

9.0

10.0

11.0

V

VCC=5V

2.9

3.33

3.8

2.6

3.33

4.0

V

VCC=15V

9.4

10.0

10.6

8.8

10.0

11.2

V

VCC=5V

2.7

3.33

4.0

2.4

3.33

4.2

V

0.1

0.25

0.1

0.25

µA V

VCC=15V

4.8

5.0

5.2

4.5

5.0

5.6

VCC=5V

1.45

1.67

1.9

1.1

1.67

2.2

V

0.5

0.9

0.5

2.0

µA

ITRIG

Trigger current

VTRIG=0V

VRESET

Reset voltage4

VCC=15V, VTH =10.5V

1.0

V

IRESET

Reset current

VRESET=0.4V

0.1

0.4

0.1

0.4

mA

Reset current

VRESET=0V

0.4

1.0

0.4

1.5

mA

ISINK=10mA

0.1

0.15

0.1

0.25

V

ISINK=50mA

0.4

0.5

0.4

0.75

V

ISINK=100mA

2.0

2.2

2.0

2.5

V

ISINK=200mA

2.5

0.3

1.0

0.3

VCC=15V

VOL

Output voltage (low)

2.5

V

VCC=5V ISINK=8mA

0.1

0.25

0.3

0.4

V

ISINK=5mA

0.05

0.2

0.25

0.35

V

VCC=15V ISOURCE=200mA VOH

Output voltage (high)

ISOURCE=100mA

12.5 13.0

13.3

3.0

3.3

12.5

V

12.75

13.3

V

2.75

3.3

VCC=5V ISOURCE=100mA

V

0.5

2.0

0.5

2.0

µs

Rise time of output

100

200

100

300

ns

Fall time of output

100

200

100

300

ns

Discharge leakage current

20

100

20

100

nA

tOFF

Turn-off time5

tR tF

VRESET=VCC

NOTES: 1. Supply current when output high typically 1mA less. 2. Tested at VCC=5V and VCC=15V. 3. This will determine the max value of RA+RB, for 15V operation, the max total R=10MΩ, and for 5V operation, the max. total R=3.4MΩ. 4. Specified with trigger input high. 5. Time measured from a positive going input pulse from 0 to 0.8×VCC into the threshold to the drop from high to low of the output. Trigger is tied to threshold.

August 31, 1994

349



Timer

NE/SA/SE555/SE555C

TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Supply Voltage

150

10.0

125

8.0

-55oC

100

0 oC 75 +25oC +70oC

50 25

1.015 +125oC +25oC

6.0 -55oC 4.0

2.0

+125oC

0

1.005 1.000 0.995

0.990

0.1

0.2

0.3

0.985 5.0

0.4 (XVCC)

10.0

15.0

-50 -25

SUPPLY VOLTAGE – VOLTS

LOWEST VOLTAGE LEVEL OF TRIGGER PULSE

Low Output Voltage vs Output Sink Current

VCC = 15V

-55oC

+25oC 0.1

0.001

1.0 -55oC

+25oC +25oC

+25oC 0.1

V OUT – VOLTS

V OUT – VOLTS

+25oC

+25oC -55oC

2.0

5.0

10

20

50

100

+25oC

0.1 +25oC

55oC

0.01

0.01

1.0

1.0

2.0

5.0

ISINK – mA

10

20

50

1.0

100

2.0

5.0

ISINK – mA

High Output Voltage Drop vs Output Source Current

10

20

50

100

ISINK – mA

Delay Time vs Supply Voltage

2.0

+75 +100 +125

10 VCC = 10V

1.0 -55oC

+25 +50


10 VCC = 5V

1.0

0

TEMPERATURE – oC


10

V OUT – VOLTS

1.010

0

0

Propagation Delay vs Voltage Level of Trigger Pulse

1.015

300

1.010

250

+25oC

1.4 1.2

+125oC

1.0 0.8 0.6 0.4

PROPAGATION DELAY – ns

1.6

NORMALIZED DELAY TIME

–55oC

1.8

V CC V OUT – VOLTS

Delay Time vs Temperature

NORMALIZED DELAY TIME

SUPPLY CURRENT – mA

MINIMUM PULSE WIDTH (ns)

Minimum Pulse Width Required for Triggering

1.005 1.000 0.995 0.990

-55oC 200 0 oC 150 100

+25oC +70oC

50 +25oC

5V ≤ VCC ≤ 15V

0.2

0.985

0 1.0

2.0

5.0

10

20

ISOURCE – mA

August 31, 1994

50

100

0 0

5

10

15

SUPPLY VOLTAGE – V

350

20

0

0.1

0.2

0.3

LOWEST VOLTAGE LEVEL OF TRIGGER PULSE – XVCC

0.4



Timer

NE/SA/SE555/SE555C

TYPICAL APPLICATIONS VCC

RA

555 OR 1/2 556

8 7

DISCHARGE

R

RB 5

CONTROL VOLTAGE .01µF

COMP

6

THRESHOLD

3

FLIP FLOP

R

OUTPUT OUTPUT

COMP

2 TRIGGER

R

f

C 4

1.49 (R A 2R B)C

RESET

Astable Operation VCC

RA

555 OR 1/2 556

8 DISCHARGE

7

CONTROL VOLTAGE

5

R

.01µF

| ∆t |

COMP

6

THRESHOLD C

FLIP FLOP

R

3 OUTPUT OUTPUT

COMP

2 TRIGGER

1 V 3 CC

R

4 RESET

Monostable Operation

August 31, 1994

351

∆T = 1.1RC



Timer

NE/SA/SE555/SE555C

TYPICAL APPLICATIONS

VCC VCC

VCC

10k 1/3 VCC

.001µF 2

555 OVOLTS

1 DURATION OF TRIGGER PULSE AS SEEN BY THE TIMER

NOTE: All resistor values are in Ω

SWITCH GROUNDED AT THIS POINT

Figure 1. AC Coupling of the Trigger Pulse

Trigger Pulse Width Requirements and Time Delays

Another consideration is the “turn-off time”. This is the measurement of the amount of time required after the threshold reaches 2/3 VCC to turn the output low. To explain further, Q1 at the threshold input turns on after reaching 2/3 VCC, which then turns on Q5, which turns on Q6. Current from Q6 turns on Q16 which turns Q17 off. This allows current from Q19 to turn on Q20 and Q24 to given an output low. These steps cause the 2µs max. delay as stated in the data sheet.

Due to the nature of the trigger circuitry, the timer will trigger on the negative going edge of the input pulse. For the device to time out properly, it is necessary that the trigger voltage level be returned to some voltage greater than one third of the supply before the time out period. This can be achieved by making either the trigger pulse sufficiently short or by AC coupling into the trigger. By AC coupling the trigger, see Figure 1, a short negative going pulse is achieved when the trigger signal goes to ground. AC coupling is most frequently used in conjunction with a switch or a signal that goes to ground which initiates the timing cycle. Should the trigger be held low, without AC coupling, for a longer duration than the timing cycle the output will remain in a high state for the duration of the low trigger signal, without regard to the threshold comparator state. This is due to the predominance of Q15 on the base of Q16, controlling the state of the bi-stable flip-flop. When the trigger signal then returns to a high level, the output will fall immediately. Thus, the output signal will follow the trigger signal in this case.

August 31, 1994

Also, a delay comparable to the turn-off time is the trigger release time. When the trigger is low, Q10 is on and turns on Q11 which turns on Q15. Q15 turns off Q16 and allows Q17 to turn on. This turns off current to Q20 and Q24, which results in output high. When the trigger is released, Q10 and Q11 shut off, Q15 turns off, Q16 turns on and the circuit then follows the same path and time delay explained as “turn off time”. This trigger release time is very important in designing the trigger pulse width so as not to interfere with the output signal as explained previously.

352

Jobsheet Praktikum REGISTER

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